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IDProjectCategoryView StatusLast Update
0026089FPCCompilerpublic2014-12-07 22:10
Reporterlagprogramming Assigned ToFlorian  
PrioritynormalSeverityfeatureReproducibilityalways
Status resolvedResolutionno change required 
Product Version2.6.2 
Summary0026089: Slow code generated for if...then...else
DescriptionTake a look at the following function:

function q(var x,c:integer):integer;
begin
if c=x then
  Result:=1
else
  Result:=0;
end;

   If the function is called when x=c, then the code takes longer than when it is called with x<>c. This is not good because the "then" part should be executed faster than the "else" part.
   Also, if x=c, when not optimized, the code runs faster than when having level 1, 2 or 3 optimizations.

   If the same function is declared like one of the following two lines then everything is fine("then" part is executed faster then "else" part and turning on optimizations leads to faster code execution):
function q(x,c:integer):integer;
function q(const x,c:integer):integer;
Additional InformationThis happens with both 2.6.2 and 2.6.4.
The attachment contains an example: set values '2' and '3' in the tedit and click the test tbutton to see the elapsed time.
TagsNo tags attached.
Fixed in Revision
FPCOldBugId
FPCTarget
Attached Files

Activities

lagprogramming

2014-04-28 18:04

reporter  

inefficientcode.zip (129,210 bytes)

Jonas Maebe

2014-04-28 22:59

manager   ~0074648

Last edited: 2014-04-28 22:59

View 2 revisions

> Also, if x=c, when not optimized, the code runs faster than
> when having level 1, 2 or 3 optimizations.

In that case, you are obviously running into a situation where you have a useless micro-benchmark. That can happen due to code size differences resulting in different alignment, cache access patterns etc. It will probably also depend on which processor you are running on.

Additionally, if you compile your code with -Cppentiumm or so, it will be compiled into assembly without any branches at all and it doesn't matter which branch is there first.

FPC currently assumes that the programmer knows best which outcome is likely, it does not implement any heuristics. If it would, then we would also have to add intrinsics that allow the programmer to override those heuristics because you can bet that the next bug report will be "my code was faster with FPC 2.6.x than with FPC 2.7.x, because it used to respect my order of if/then/else and now it doesn't anymore").

Jonas Maebe

2014-04-28 23:11

manager   ~0074649

> In that case, you are obviously running into a situation where you have a useless micro-benchmark.

Well, it can also be due to the fact that without optimizations on, the fall-through path is the "else"-branch.

Thaddy de Koning

2014-04-29 15:45

reporter   ~0074660

Last edited: 2014-04-29 15:48

View 3 revisions

The likelihood that x=c is unlikely similar to x<>c thus can not be optimized the way you want. At best it is 1/3 to 2/3. This is up to the programmer.
Unless you have a magical mathematical proof ;-)

Jonas Maebe

2014-04-29 15:56

manager   ~0074661

It's not about mathematical proof, it's a heuristic that has been shown to work well in practice: http://research.microsoft.com/en-us/um/people/tball/papers/pldi93.pdf

But as mentioned, if you do that then you should probably also provide a way for programmers to override it (at least in the Delphi/FPC world, where many programmers want a lot of control over the details of the generated code).

lagprogramming

2014-04-29 17:53

reporter   ~0074667

I feel like I didn't explained the problem well enough so I present the following three situations:

SITUATION 1:
function q(x,c:integer):integer;
 begin
 if c=x then Result:=1 else Result:=0;
 end;

With level 0 optimizations q(2,2) is executed faster than q(2,3);
With level 2 optimizations q(2,2) is executed faster than q(2,3);
q(2,2) with level 2 optimizations is executed faster than q(2,2) with level 0 optimizations;
q(2,3) with level 2 optimizations is executed faster than q(2,3) with level 0 optimizations;


SITUATION 2:
function q(const x,c:integer):integer;//NOTICE THE ADDITION OF "CONST"!!!
 begin
 if c=x then Result:=1 else Result:=0;
 end;

With level 0 optimizations q(2,2) is executed faster than q(2,3);
With level 2 optimizations q(2,2) is executed faster than q(2,3);
q(2,2) with level 2 optimizations is executed faster than q(2,2) with level 0 optimizations;
q(2,3) with level 2 optimizations is executed faster than q(2,3) with level 0 optimizations;


SITUATION 3:
HERE IS THE PROBLEM!

function q(var x,c:integer):integer;//NOTICE THE ADDITION OF "VAR"!!!
 begin
 if c=x then Result:=1 else Result:=0;
 end;

With level 0 optimizations q(2,2) is executed SLOWER than q(2,3);I EXPECT TO BE EXECUTED FASTER AS IN PREVIOUS SITUATIONS.
With level 2 optimizations q(2,2) is executed SLOWER than q(2,3);I EXPECT TO BE EXECUTED FASTER AS IN PREVIOUS SITUATIONS.
q(2,2) with level 2 optimizations is executed SLOWER than q(2,2) with level 0 optimizations;I EXPECT TO BE EXECUTED FASTER AS IN PREVIOUS SITUATIONS.
q(2,3) with level 2 optimizations is executed faster than q(2,3) with level 0 optimizations;IT'S OK! SAME AS IN THE PREVIOUS SITUATIONS.

Jonas Maebe

2014-04-29 18:19

manager   ~0074669

That is exactly the situation that I mentioned before: a useless microbenchmark. The code generated with -O2 for your "situation 3" is objectively better than the one for -O-: fewer instructions, fewer memory accesses. If it's still slower, that means that secondary effects are affecting the run time such as cache line conflicts or plain black magic.

Nobody today is able to write compilers that generate optimal code for modern processors under all circumstances. Have a look at e.g. http://research.google.com/pubs/pub37077.html , where they discovered that inserting random "nop" instructions in code could gain them up to 10% speed increase, even *after* they eliminated obvious cases of cache line conflicts. Afaik, nobody has been able yet to explain where that speed increase is coming from.

Florian

2014-04-29 20:27

administrator   ~0074674

Last edited: 2014-04-29 20:31

View 4 revisions

Just a note: on my i7-4770, the -O3 variant is the fastest and x=c is faster (~ 10 %) than x<>c in this case.

> Afaik, nobody has been able yet to explain where that speed increase is coming from.

Isn't it due to branch prediction? Afaik most older CPUs can trace only one branch per 16 byte.

I agree with Jonas: this is a micro benchmark without any practical use. But I didn't close the bug yet because the peephole optimizer could transform the jmp/ret into a ret. But I wouldn't expect that this improves the situation.

lagprogramming

2014-09-10 15:45

reporter   ~0077052

Last edited: 2014-09-10 16:14

View 2 revisions

This comment is added because I might use this report as a reference in the future.


function fastexecution(x,c:integer):integer;
Begin
Result:=0;//When X=2*C this predefined assignment is useless. The only thing that differs between the two functions is the position of this line.
while x<10 do
      begin
      if x div 2 = C then exit(x);
      inc(x);
      end;
end;

function slowexecution(x,c:integer):integer;
begin
while x<10 do
      begin
      if x div 2 = C then exit(x);
      inc(x);
      end;
Result:=0;//The only thing that differs between the two functions is the position of this line.
end;

Execution time for slowexecution(0,8) is similar to fastexecution(0,8);
Execution time for slowexecution(0,1) is ~(136%) fastexecution(0,1);
The CPU used for these tests is Mobile AMD Sempron(tm) Processor 3500+ with target x86_64.

lagprogramming

2014-09-10 20:06

reporter   ~0077067

Last edited: 2014-09-11 12:13

View 3 revisions

This comment is added because I might use this report as a reference in the future.

"fast" and "slow" at the beginning of the functions are linked to the use of longint variables. Changing the variables to int64 makes the "slow" function behave "fast" and the "fast" one behave "slow".

function fastexecution(x,c:longint):longint;
function fastexecution(x,c:int64):int64;//This declaration will make the code slower than the int64 version of "slowexecution".
Begin
Result:=0;//When X=2*C this predefined assignment is useless. The only thing that differs between the two functions is the position of this line.
while x<10 do
      begin
      if x div 2 = C then exit(x);
      inc(x);
      end;
end;

function slowexecution(x,c:longint):longint;
function slowexecution(x,c:int64):int64;//This declaration will make the code faster than the int64 version of "fastexecution".
begin
while x<10 do
      begin
      if x div 2 = C then exit(x);
      inc(x);
      end;
Result:=0;//The only thing that differs between the two functions is the position of this line.
end;



procedure TForm1.Button1Click(Sender: TObject);
VAR Z,X,C,r:int64;
    M:DWORD;
begin
M:=GETTICKCOUNT;
C:=STRTOINT64(EDIT1.TEXT);//Use a value from a textbox in order to make sure the generated code will not be optimized for particular values.
r:=0;
FOR Z:=0 TO 50000000 DO
    BEGIN
    slowexecution(0,1);
    end;
M:=GETTICKCOUNT-M;
BUTTON1.Caption:='Elapsed time is '+INTTOSTR(M)+'ms. r='+inttostr(r);
end;
Execution time for fastexecution(0,8) is ~8600ms.
Execution time for slowexecution(0,8) is ~6800ms.

Execution time for fastexecution(0,1) is ~4100ms.
Execution time for slowexecution(0,1) is ~2400ms.


The CPU used for these tests is Mobile AMD Sempron(tm) Processor 3500+ with target x86_64.

There might be an assumption for x86_64 target: Doubling the amount of memory occupied by integers has a bigger impact than the speed increase of using native(64bit) integers.
I think there might be 64bit processors(under x86_64) that don't follow the above assumption. The CPU mentioned above might be one of these.
The analysis within this bug report sustains my hypothesis.
The only thing that needs proof is the boolean evaluation. I think that this boolean evaluation is also designed for 32bit, reason why we meet this anomalies.
Due to the fact that I don't have reasons to believe that the mentioned CPU is the only processor in this situation a mailing list discussion might be started.

Even if the hypothesis is wrong, we already have a partial workaround(due to the longint(integer)-int64 use that leads to slow execution speed pattern) that might request an additional target processor for x86_64.

Do-wan Kim

2014-09-11 03:20

reporter   ~0077076

I'm using Llano processor and fpc 2.7.1.

In assembly code, there is no different in if-else codes.
Only one thing is different is return value assignment. If no return value assignment, no difference.

I think this code is key assembly codes of difference.

000000000045C049 48c745e800000000 movq $0x0,-0x18(%rbp)
ifelse_main.pas:51 end;
000000000045C051 488b45e8 mov -0x18(%rbp),%rax

lagprogramming

2014-09-11 14:35

reporter   ~0077083

http://stackoverflow.com/questions/17896714/why-would-introducing-useless-mov-instructions-speed-up-a-tight-loop-in-x86-64-a
Still, I might not know when to give up. :)

lagprogramming

2014-09-13 18:45

reporter  

AMDSempronMobile3500pluswine (2,319 bytes)   
Inc(r,q_longint(0,0)); 6849ms;6469ms;6494ms
Inc(r,q_longint(0,1)); 7057ms;7049ms;7177ms
Inc(r,q_longint_inline(0,0)); 3233ms;3273ms;3177ms
Inc(r,q_longint_inline(0,1)); 3870ms;3905ms;3905ms
Inc(r,q_var_longint(0,0)); 14251ms;14318ms;14304ms***
Inc(r,q_var_longint(0,1)); 5789ms;5787ms;5820ms
Inc(r,q_var_longint_inline(0,0)); 3869ms;3905ms;3909ms
Inc(r,q_var_longint_inline(0,1)); 3793ms;3818ms;3907ms
Inc(r,q_constref_longint(0,0)); 14901ms;14913ms;14952ms***
Inc(r,q_constref_longint(0,1)); 6500ms;6540ms;6447ms
Inc(r,q_constref_longint_inline(0,0)); 3796ms;3806ms;3883ms
Inc(r,q_constref_longint_inline(0,1)); 3863ms;3900ms;3806ms
Inc(r,q_const_longint(0,0)); 9464ms;8898ms;8985ms
Inc(r,q_const_longint(0,1)); 10132ms;11163ms;9514ms
Inc(r,q_const_longint_inline(0,0)); 2602ms;2641ms;2639ms
Inc(r,q_const_longint_inline(0,1)); 2528ms;2538ms;2537ms
Inc(r,q_int64(0,0)); 10981ms;11132ms;11008ms
Inc(r,q_int64(0,1)); 9696ms;9694ms;9738ms
Inc(r,q_int64_inline(0,0)); 4524ms;4541ms;4540ms
Inc(r,q_int64_inline(0,1)); 3897ms;3903ms;3907ms
Inc(r,q_var_int64(0,0)); 16131ms;16213ms;16260ms***
Inc(r,q_var_int64(0,1)); 12005ms;14454ms;14775ms*****
Inc(r,q_var_int64_inline(0,0)); 3796ms;3904ms;3881ms
Inc(r,q_var_int64_inline(0,1)); 4526ms;4544ms;4550ms
Inc(r,q_constref_int64(0,0)); 15542ms;16037ms;15569ms***
Inc(r,q_constref_int64(0,1)); 5893ms;5811ms;5782ms
Inc(r,q_constref_int64_inline(0,0)); 4527ms;4517ms;4516ms
Inc(r,q_constref_int64_inline(0,1)); 4429ms;4539ms;4512ms
Inc(r,q_const_int64(0,0)); 11054ms;11024ms;10991ms
Inc(r,q_const_int64(0,1)); 9764ms;9785ms;9716ms
Inc(r,q_const_int64_inline(0,0)); 3802ms;3907ms;3895ms
Inc(r,q_const_int64_inline(0,1)); 4524ms;4542ms;4529ms

A Mobile AMD Sempron(tm) Processor 3500+ was used, level 2 optimizations, targetos(win32), target CPU family(i386), target processor(default), CPU speed set fixed to 800MHz. Timings were taken using wine.

Observations:
1)Abnormal timings were observed for(***):
Inc(r,q_var_longint(0,0));
Inc(r,q_constref_longint(0,0));
Inc(r,q_var_int64(0,0));
Inc(r,q_constref_int64(0,0));
Timings consistent with those for x86_64 target except for the presence of Inc(r,q_var_int64(0,1));

Things these functions share:
All these functions use "jne".
Parameters are passed by referrence.

2)An exception appeared for(*****):
Inc(r,q_var_int64(0,1));
AMDSempronMobile3500pluswine (2,319 bytes)   

lagprogramming

2014-09-13 18:45

reporter  

AMDSempronMobile3500plusx8664.txt (4,562 bytes)   
Inc(r,q_longint(0,0)); 6366ms;6374ms;6361ms;6468ms;6454ms;5785ms;5722ms
Inc(r,q_longint(0,1)); 6984ms;6962ms;7008ms;6963ms;6963ms;6355ms;6336ms
Inc(r,q_longint_inline(0,0)); 3781ms;3805ms;3795ms;3806ms;3808ms;3783ms;3808ms
Inc(r,q_longint_inline(0,1)); 3810ms;3810ms;3816ms;3811ms;3806ms;3175ms;3176ms
Inc(r,q_longint_je(0,0)); 6330ms;6329ms;6349ms;6337ms;6332ms;5706ms;5705ms
Inc(r,q_longint_je(0,1)); 6985ms;7099ms;7009ms;6986ms;6965ms;6335ms;6335ms
Inc(r,q_var_longint(0,0)); 14581ms;14577ms;14616ms;14580ms;14584ms;14576ms;14573ms***
Inc(r,q_var_longint(0,1)); 6327ms;6332ms;6351ms;6329ms;6338ms;6355ms;6331ms
Inc(r,q_var_longint_inline(0,0)); 3179ms;3154ms;3205ms;3156ms;3176ms;3781ms;3808ms
Inc(r,q_var_longint_inline(0,1)); 3781ms;3805ms;3795ms;3806ms;3810ms;3807ms;3806ms
Inc(r,q_var_longint_je(0,0)); 6378ms;6331ms;6369ms;6332ms;6330ms;6329ms;6332ms
Inc(r,q_var_longint_je(0,1)); 6960ms;6984ms;6978ms;6993ms;6963ms;6984ms;6988ms
Inc(r,q_constref_longint(0,0)); 14575ms;14575ms;14615ms;14583ms;14577ms;14574ms;14549ms***
Inc(r,q_constref_longint(0,1)); 6571ms;6333ms;6354ms;6403ms;6413ms;6359ms;6357ms
Inc(r,q_constref_longint_inline(0,0)); 3184ms;3178ms;3192ms;3178ms;3153ms;3808ms;3783ms
Inc(r,q_constref_longint_inline(0,1)); 3809ms;3781ms;3819ms;3785ms;3812ms;3781ms;3809ms
Inc(r,q_constref_longint_je(0,0)); 6331ms;6360ms;6348ms;6353ms;6335ms;6355ms;6328ms
Inc(r,q_constref_longint_je(0,1)); 6957ms;6965ms;6983ms;6962ms;6986ms;6960ms;6986ms
Inc(r,q_const_longint(0,0)); 5702ms;5697ms;5737ms;5701ms;5705ms;5697ms;5702ms
Inc(r,q_const_longint(0,1)); 6355ms;6330ms;6348ms;6353ms;6332ms;6331ms;6327ms
Inc(r,q_const_longint_inline(0,0)); 3155ms;3175ms;3160ms;3154ms;3178ms;3805ms;3812ms
Inc(r,q_const_longint_inline(0,1)); 3805ms;3808ms;3818ms;3813ms;3810ms;3809ms;3805ms
Inc(r,q_const_longint_je(0,0)); 6332ms;6331ms;6345ms;6334ms;6331ms;5702ms;5708ms
Inc(r,q_const_longint_je(0,1)); 6983ms;6983ms;7004ms;6990ms;6962ms;6332ms;6327ms
Inc(r,q_int64(0,0)); 5698ms;5701ms;5716ms;5699ms;5702ms;6987ms;6984ms
Inc(r,q_int64(0,1)); 5069ms;5068ms;5082ms;5070ms;5068ms;6336ms;6337ms
Inc(r,q_int64_inline(0,0)); 4445ms;4459ms;4455ms;4439ms;4438ms;4436ms;4438ms
Inc(r,q_int64_inline(0,1)); 3809ms;3781ms;3816ms;3785ms;3812ms;3808ms;3805ms
Inc(r,q_int64_je(0,0)); 6960ms;6994ms;6982ms;6986ms;6962ms;6961ms;6979ms
Inc(r,q_int64_je(0,1)); 6961ms;6960ms;6980ms;6980ms;6985ms;6985ms;6963ms
Inc(r,q_var_int64(0,0)); 15858ms;15854ms;15915ms;15855ms;15886ms;15204ms;15210ms***
Inc(r,q_var_int64(0,1)); 6985ms;6986ms;6980ms;6988ms;6963ms;7081ms;7192ms
Inc(r,q_var_int64_inline(0,0)); 3809ms;3781ms;3821ms;3788ms;3806ms;3178ms;3151ms
Inc(r,q_var_int64_inline(0,1)); 4438ms;4437ms;4451ms;4440ms;4440ms;3151ms;3179ms
Inc(r,q_var_int64_je(0,0)); 6367ms;6378ms;6405ms;7057ms;7048ms;5701ms;5704ms
Inc(r,q_var_int64_je(0,1)); 7032ms;7161ms;7111ms;8305ms;7771ms;6360ms;6330ms
Inc(r,q_constref_int64(0,0)); 14608ms;14602ms;14641ms;14595ms;14592ms;15855ms;15854ms***
Inc(r,q_constref_int64(0,1)); 5072ms;5067ms;5330ms;5068ms;5076ms;6327ms;6359ms
Inc(r,q_constref_int64_inline(0,0)); 4438ms;4437ms;4676ms;4439ms;4440ms;4438ms;4438ms
Inc(r,q_constref_int64_inline(0,1)); 3805ms;3809ms;3816ms;3809ms;3806ms;3809ms;3781ms
Inc(r,q_constref_int64_je(0,0)); 6960ms;6959ms;7027ms;6969ms;6963ms;6960ms;6985ms
Inc(r,q_constref_int64_je(0,1)); 7004ms;6962ms;6983ms;6988ms;6961ms;6985ms;6961ms
Inc(r,q_const_int64(0,0)); 6960ms;6984ms;7040ms;6961ms;6986ms;6347ms;6345ms
Inc(r,q_const_int64(0,1)); 6963ms;6961ms;7013ms;6986ms;6964ms;6356ms;6372ms
Inc(r,q_const_int64_inline(0,0)); 3806ms;3807ms;3784ms;3793ms;3810ms;3177ms;3161ms
Inc(r,q_const_int64_inline(0,1)); 4449ms;4453ms;4450ms;4441ms;4450ms;3160ms;3187ms
Inc(r,q_const_int64_je(0,0)); 6520ms;6405ms;6373ms;6540ms;7296ms;5711ms;5705ms
Inc(r,q_const_int64_je(0,1)); 7146ms;7058ms;7149ms;7295ms;7470ms;6375ms;6330ms

Computer was restarted after first 3 sets of timings, then restarted again after the following 2 sets. After that, minor modifications have been made to the program and additional two sets were added.
A Mobile AMD Sempron(tm) Processor 3500+ was used, level 2 optimizations, targetos(default={linux}), target CPU family(x86_64), target processor(default), CPU speed set fixed to 800MHz.

Observations:
1)Abnormal timings were observed for(***):
Inc(r,q_var_longint(0,0));
Inc(r,q_constref_longint(0,0));
Inc(r,q_var_int64(0,0));
Inc(r,q_constref_int64(0,0));

Things these functions share:
1)All these functions use "jne". Not a single abnormal value was observed for "_je" functions.
2)Parameters are passed by referrence.

lagprogramming

2014-09-13 18:46

reporter  

ifthenelse.zip (5,620 bytes)

lagprogramming

2014-09-13 19:16

reporter  

IntelAtomCPUN2701.60GHzi386.txt (2,219 bytes)   
Inc(r,q_longint(0,0)); 5141ms;5125ms;5422ms
Inc(r,q_longint(0,1)); 4812ms;4813ms;5734ms
Inc(r,q_longint_inline(0,0)); 2000ms;1984ms;2610ms
Inc(r,q_longint_inline(0,1)); 2297ms;2359ms;2469ms
Inc(r,q_var_longint(0,0)); 3375ms;3313ms;3531ms
Inc(r,q_var_longint(0,1)); 5078ms;5078ms;5109ms
Inc(r,q_var_longint_inline(0,0)); 2719ms;2750ms;2719ms
Inc(r,q_var_longint_inline(0,1)); 2625ms;2641ms;3312ms
Inc(r,q_constref_longint(0,0)); 3640ms;3672ms;4672ms
Inc(r,q_constref_longint(0,1)); 5157ms;5125ms;5266ms
Inc(r,q_constref_longint_inline(0,0)); 2640ms;2640ms;3656ms
Inc(r,q_constref_longint_inline(0,1)); 2641ms;2656ms;3281ms
Inc(r,q_const_longint(0,0)); 5156ms;5093ms;5204ms*****
Inc(r,q_const_longint(0,1)); 3640ms;3641ms;4812ms
Inc(r,q_const_longint_inline(0,0)); 2000ms;2000ms;2844ms
Inc(r,q_const_longint_inline(0,1)); 1750ms;1719ms;2219ms
Inc(r,q_int64(0,0)); 14766ms;14844ms;18672ms***
Inc(r,q_int64(0,1)); 13843ms;13859ms;19438ms***
Inc(r,q_int64_inline(0,0)); 4063ms;4047ms;4968ms
Inc(r,q_int64_inline(0,1)); 3328ms;3281ms;3609ms
Inc(r,q_var_int64(0,0)); 5031ms;5063ms;5578ms
Inc(r,q_var_int64(0,1)); 4969ms;4953ms;5938ms
Inc(r,q_var_int64_inline(0,0)); 3703ms;3734ms;3766ms
Inc(r,q_var_int64_inline(0,1)); 4015ms;4016ms;4328ms
Inc(r,q_constref_int64(0,0)); 4907ms;4953ms;7703ms
Inc(r,q_constref_int64(0,1)); 5000ms;4954ms;10234ms*
Inc(r,q_constref_int64_inline(0,0)); 4000ms;4015ms;5078ms
Inc(r,q_constref_int64_inline(0,1)); 3703ms;3719ms;5203ms
Inc(r,q_const_int64(0,0)); 14938ms;14812ms;16704ms***
Inc(r,q_const_int64(0,1)); 13922ms;14485ms;15406ms***
Inc(r,q_const_int64_inline(0,0)); 3625ms;3812ms;3797ms
Inc(r,q_const_int64_inline(0,1)); 4015ms;4235ms;4140ms

An Intel Atom CPU N270 1.60GHz was used, level 2 optimizations, targetos(win32), target CPU family(i386), target processor(default), CPU governor could not be set to fixed speed. Binary built in wine, timings taken in windows.

Observations:
1)Regarding timings(***), should be noted that these appear using int64 variables on a 32bit CPU.
2)Regarding one timing(*), maybe the CPU got too hot.
3)A single abnormal function timing(*****) has been recorded but the situation is nowhere near AMD Sempron's.


Do-wan Kim

2014-09-14 23:22

reporter   ~0077247

fastcode func,
assign stack result to 0, func body, stack result to edx:eax.

slow func,
funcbody, assign stack result to 0, stack result to edx:eax.

lagprogramming

2014-09-26 10:51

reporter   ~0077680

Last edited: 2014-09-26 10:52

View 2 revisions

This comment is added because I might use this report as a reference in the future.

procedure aaa(x,c:longint);
begin if c=0 then exit;x:=c;end;

procedure bbb(x,c:longint);
begin if c<>0 then x:=c;end;

   Code produced differs in term of registers used. Within procedures/functions with lots of variables/loops a simple "exit" removal leads to speed drop(at least using particular CPUs). Looking within Fpc/Lazarus sources use of "exit" procedure at the very beginning is a common programming practise.

Assembly extras of "aaa" and "bbb" procedures(x86_64 target):

.globl UNIT1_AAA$LONGINT$LONGINT
    .type UNIT1_AAA$LONGINT$LONGINT,@function
UNIT1_AAA$LONGINT$LONGINT:
# Temps allocated between rsp+0 and rsp+0
# Var x located in register eax
# Var c located in register esi
# [unit1.pas]
# [62] begin
.Ll1:
# [63] if c=0 then exit;x:=c;
    movl %esi,%eax
    testl %eax,%eax
    je .Lj3
    movl %esi,%eax
.Lj3:
.Ll2:
# [64] end;
    ret
.Lt1:
.Le0:
    .size UNIT1_AAA$LONGINT$LONGINT, .Le0 - UNIT1_AAA$LONGINT$LONGINT
.Ll3:

.section .text
    .balign 8,0x90
.globl UNIT1_BBB$LONGINT$LONGINT
    .type UNIT1_BBB$LONGINT$LONGINT,@function
UNIT1_BBB$LONGINT$LONGINT:
# Temps allocated between rsp+0 and rsp+0
# Var x located in register edi
# Var c located in register esi
# [67] begin
.Ll4:
# [68] if c<>0 then x:=c;
    movl %esi,%eax
    testl %eax,%eax
    je .Lj12
    movl %esi,%edi
.Lj12:
.Ll5:
# [69] end;
    ret
.Lt2:
.Le1:
    .size UNIT1_BBB$LONGINT$LONGINT, .Le1 - UNIT1_BBB$LONGINT$LONGINT



An additional test has been done:
inserted "x:=c-1;" as first line within the two procedures(also useful for the 2014-09-11 14:35 note). This lead to same registers used by the "x" and "c" variables, but the registers used within the code were different between the procedures. This means that most probably the presence of "exit" procedure has an influence on the registers used, it's not like "exit" would be equivalent to a jump at the end of the function/procedure as it's presence messes with registers. This would be contrary to:
"The Exit call sets the result of the function and jumps to the final End of the function declaration block. It can be seen as the equivalent of the C return instruction.", extras from "14.3 Function results" of reference guide.

Jonas Maebe

2014-09-26 11:24

manager   ~0077681

The language manual talks about semantics. The implementation details of the code generator and register allocator are completely unrelated to that and can change at any time.

Additionally, please don't use this bug report as your personal wiki for case studies of FPC code generation. That is not what the bug reporting system is for (it's to report one concrete issue at a time that can be individually addressed), and at some point the bug will be closed in which case you can no longer add comments for future reference anymore.

lagprogramming

2014-09-26 18:58

reporter   ~0077705

FOREWORD

   When I introduce a note with "personal" word at the beginning, I do it because I know most of you(not everybody) are not interested in the subject. I announce most of you from the very beginning that reading the note won't bring you joy and happiness. I find this a fair attitude, an attitude contrary to the "do this to...whatever I think you might like".

   IF YOU DON'T WANT ME TO STOP APPENDING INFORMATIONS TO THIS TICKET PLEASE CLEARLY ASK SO, I'LL DO MY BEST TO FOLLOW YOUR WISH!
   FROM NOW ONE YOU CAN SKIP THE REST OF THE NOTE AS IT'S A SUMMARY OF GOOD THINGS THAT HAPPENED HERE!!!



   I. INTRODUCTION

   A "personal" clarification is needed. This is "personal" for each and every "ENTITY"(programmer,developer,architect,end-user....) that doesn't want to waste resources. Speed is a very important factor for many of these "entities". It's far from being a top priority for everybody and this aspect won't change in the future. Still, many "entities" would dream to see pascal(fpc, including fpc compiled applications, in particular) faster than common C compilers. At this moment we are very far from that. Remember that "..we already have a faster move procedure..." affirmation!? It gave hope. There are so many areas to be improved, you won't believe it, not just speed. So, when you read "personal" in the notes let's make it clear...it's "personal" for more than one "entity", not just me.
   Regarding speed, comparing fpc with C compiled applications is a total nonsense for now. But I still have this dream. Before we can compare our programs with C ones let's compare with Delphi ones. Delphi would be an intermediate step, a step closer, a step that more people would believe in. If there is something fpc/lazarus can beat Delphi with smallest efforts, in my point of view that thing is code execution speed. Can you tell me something we are better now, except that fpc and lazarus are free up to a "free"dom degree?! Speed would be something new for us, something new to be ahead of delphi, something that we can proudly state. Smile with me if you dream to achieve this intermediate step: :) "JONAS...DON'T CURSE!!! :) SMILE"


   II. THIS BUG REPORT IMPORTANCE

1) Don't read it literally. It's not just about "if...then...else" statements. It's about conditional jumps. This means that the bug refers to "if", "for", "while", "repeat", "case"....statements, each and every one of them. Each and every such statement can be a bottleneck regarding speed of code execution. This means that, as stated in a preview note, many "entities" don't realize they face this anomaly...this huge slowdown. Also, it's not known how many CPUs are affected, models or number. I also think this ticket has the potential to surface other things that have a beneficial impact not just on speed. For example, when trying to increase speed a "code analysis might be needed". Do you have any ideas how many "getmems" we have without(or with partial) "if getmempointer{<>,=}nil..." but with plenty of other error raise statements? As an additional example regarding necessity of code reanalysis, some people complain regarding ansistrings speed, "maybe" the following code will improve their programs: "Pointer(Temp) := NewAnsiString(Length(Source)+LS);SetLength(Temp,Length(Source)+LS);"?! ;) WINK

2) Blaming CPU cache doesn't stand a chance, in my point of view. I agree that cache has an influence, often enough in a worse direction, but I totally disagree with accepting such differences of speed execution..."then" block two-three times slower than "else" part(part that should have been executed slower), especially when we can reproduce the situations! I find that the presented "case studies" some people disagreed are an approach to the solution of the ticket. The ticket is opened, now, due to the fact that Florian "didn't close the bug yet because the peephole optimizer could transform the jmp/ret into a ret". REMOVE THE "jne" FOR A NEW CPU TARGET "MOBILE SEMPRON" AND YOU CAN CLOSE THE BUG FORGETTING ABOUT FLORIAN'S "RET". BUT QUESTIONS WOULD REMAIN...WHAT ABOUT COMPARISONS WITH ZERO, ARE WE SURE THAT THERE ARE NO ANOMALIES THERE?! HOW MANY FUNCTIONS/PROCEDURES START WITH COMPARING A POINTER WITH NIL?! HOW MANY CPUS PRESENT THIS ANOMALY, IS YOURS ONE OF THEM?! WHAT ABOUT "LESS THAN" OR OTHER CONDITIONAL JUMPS?!
   Let me continue with "useless microbenchmark" remarks. Do you think the examples presented are too "slim"?! OK!!! This means that somebody considers that the simplicity of the functions/procedures presented is a reason to ignore the results. I can give you examples of many big functions/procedures that start with if{raise error code} else {do what the function/procedure is intended to do code} where changing the order leads to huge speed slowdowns. You can't blame the simplicity of the presented codes for such results. Imagine the speed impact of rearranging "if...then..else" code within heap.inc, dynarr.inc. Remember: two-three times time execution speed. Are you sure the code in these files is arranged "optimum"? What makes you so sure that your CPU doesn't have a single "spike" like the one I've presented for AMD's Mobile Sempron?! If you have such an anomaly...aren't you at least curious to see what is the speed improvement of the same pascal code found there in the fpc/lazarus source file. I've seen the differences on a computer: HUUUUGE!!! I change the order of a if...then...else statement by negating the condition simultaneous with switching the "then" block with "else" block: 4% speed decrease with this single(only) change.

3) This bug report already has the most "complete" analysis that I could find on the internet for pascal compilers. I see in this ticket the potential to either:
a) Expand fpc in a possible not good enough way regarding speed. What if in the future we'll see that fpc needs major changes due to things related to this bug report?!
b) Improve fpc so that it will have a chance to compete in terms of code execution speed with delphi...at least.
   These "case studies" are soooo important in my point of view...you can't understand my happiness finding the link at note 2014-09-11 14:35. I might be happy as a fool but that link gave me hope that fpc is not the only one that "suffers" from these anomalies. To me this means that there might be a chance for fpc to make a difference. It's an opportunity to differentiate of other pascal compilers in terms of speed. The fact that many of you don't believe in fpc "entities" resources to make a difference in terms of speed doesn't mean that we don't have this opportunity!
   Note: Don't ask for compiler comparison code examples. Clean the house before pointing to someone else's. This report might be just a spark. It may have been closed by the time I write this text. Did you knew that when using "while" instead of "for", at least sometimes, code is not optimized to compare with zero? I wonder if there are ways to optimize loops with 1 or -1...?! These are things that won't surface due to the attitude of some people involved, one way or another...things that I would not start a discussion due to..."local experience". ;)

4) Not applying a way to deal with these conditional jumps means that we would waste, or not improve, the potential of setting fpc targets(CPU for this matter).

5) Not applying a way to deal with these conditional jumps means that there is absolutely no hope in having consistent code execution speed increase across fpc targets. We would abandon the easiest thing we can achieve, speed(although I'm aware it's very hard to achieve).


   III. SIDE NOTES REGARDING THE COMPLEXITY OF THIS TICKET

1) My last note refers to the influence of the "exit" procedure. The fpc documentation misleads the programmer to think that "exit" is similar to declaring a label named "veryend" at the end of the function/procedure, simultaneous replacing exit with "goto veryend". Passing a parameter to the "exit" procedure is just an assignment "Result:=exitprocedureparameter;" before jumping to the "veryend" label. THIS OBVIOUS ASSUMPTION IS WRONG!!! At least at the moment I write this, even if the assembly instructions appear identical, the registers used may be different. This is obviously very hard to spot with "naked eye" when you review code, it has potential impact on speed and it was an absolutely needed breakthrough for massive "if...then...else" analysis because at the moment you can't replace "begin if {CONDITION} then exit;{SOME CODE};end;" syntax, with "begin if not({CONDITION}) then {SOME CODE}; end;" syntax. I find that simply stating this rule, is a great information because it adds a new light to the matter. In addition, there is absolutely no reference in the fpc documentation that would point to this behaviour. Regarding this ticket, some people blame unknown cpu cache behavior. Look at my second comment for this report, it contains the "exit" procedure. Nobody told me: FOOL, BE CAREFUL WITH THAT "EXIT"!!! BEWARE OF POTENTIAL DIFFERENT REGISTERS USED!!! Isn't easier to blame CPU manufacturer?! Yes, it is and it has been done in this ticket!
   Even if the ticket will be closed without solving the problem, I know that this might be the most complete ticket regarding the analysis of this matter for pascal "entities". Also, if I would have read the material pointed in this ticket somewhere before opening it, it would have saved me of lots of efforts without positive results, yet(as I still have hope). In addition, a strong point of this ticket is the way I've tried to approach the matter in a CPU independent way, although particular examples are needed to sustain affirmations.

2) Apparently fpc tries to follow gcc optimizations guide regarding levels. To some of use this means O2 are considered "safe" and O3 "not safe". Not only that my last note is an example of misunderstanding(at least) of fpc documentation but also points to how "safe" level two optimizations are.
Adding "-al" as custom options in Lazarus for the "aaa" and "bbb" procedures stated in a preview note makes assembly code identical up to level 2 optimizations. The difference starts with level 2 optimizations, a level that would have been considered "safe" but produces different and occasional worse code in terms of speed. This is something I didn't presented in the above note but something that relates to the very first explanation of the anomaly, ticket explanation where I stated that increasing optimization level leads to bigger gap in terms of speed.

3) Programmer's guide needs updates like: "for...to/downto...{zero}" is faster than "for...to/downto...{not zero}" at high optimization levels.

Sergei Gorelkin

2014-09-26 19:26

developer   ~0077707

If only I could write the compiler code at half of that rate... :sigh:

@Florian: replacing jmp/ret with ret might be not a good idea, at least on targets that make use of some kind of call frame information (e.g. DWARF CFI that's not yet in usable state, or Win64 bytecode that's working). Such systems typically expect a function to have a single entry and single exit.

EgonHugeist/ZeosDevTeam

2014-09-27 11:46

reporter   ~0077724

I would like to support reporter lagprogramming a bit.
Comparing generated code of Delphi vs. FPC and the resulting performance... You guys need some help the reporter offers. I can't help or judge in this domain.. just want to let you guys know how i feel.
 
@Sergey
Then use a define accordingly compile target?.

Florian

2014-09-27 12:17

administrator   ~0077725

> You guys need some help the reporter offers.

Well, the point is (though I assume you know this as being apparently member of the Zeos team :) ): ideas and text do not help, actually, most of the time are counter-productive because they are read by multiple people while people could code instead. Everybody has more than enough ideas. The only thing which helps is: well-written code.

EgonHugeist/ZeosDevTeam

2014-09-27 12:56

reporter   ~0077729

Last edited: 2014-09-27 13:11

View 3 revisions

@Florian

>The only thing which helps is: well-written code.
oooh this would be nice! I do understand your point of view!! But my(propably yours too) experiences are different from that. This is a dream i gave up and the reason why i joined the Zeos-Group -> just help instead of writing bad critics.

I'm trying to support most of our users WITH and WITHOUT patches. Sometimes it helps me if someone just points us to an issue we have. If the changes aren't to complex, most patches are done in a half hour by my selves. Anyway, sometimes, it's just the "idea behind" which helps too.. Which would match purpose of this report here, doesn't it?
It just the "how to" support the users i feel a bit different, but the Zeos-project isn't comparable with FPC-project, of course.

lagprogramming

2014-10-03 13:50

reporter  

AMDMobileSempronSingleSeriesTimingsWithDifferentCPUFrequencies.txt (7,762 bytes)   
   I've tried to close the ticket in a satisfying way for everybody. The ideea was to find something that would make the results(abnormal timings) totally unpredictable or very hard to be used in a satisfying way. Until now, the executable(binary executed file) has been modified, the computer was restarted and still some of the abnormal timings remained. Some of them have changed but some of them remained no matter what I've done. The only thing that could cross my mind to invalidate those remaining abnormal timings was to use different CPU frequencies.

800MHz
Inc(r,q_longint(0,0)); 17563ms***
Inc(r,q_longint(0,1)); 6594ms
Inc(r,q_longint_inline(0,0)); 4395ms
Inc(r,q_longint_inline(0,1)); 3659ms
Inc(r,q_longint_je(0,0)); 8027ms
Inc(r,q_longint_je(0,1)); 7362ms
Inc(r,q_var_longint(0,0)); 17573ms***
Inc(r,q_var_longint(0,1)); 6591ms
Inc(r,q_var_longint_inline(0,0)); 4395ms
Inc(r,q_var_longint_inline(0,1)); 4388ms
Inc(r,q_var_longint_je(0,0)); 8778ms
Inc(r,q_var_longint_je(0,1)); 8069ms
Inc(r,q_constref_longint(0,0)); 17519ms***
Inc(r,q_constref_longint(0,1)); 6574ms
Inc(r,q_constref_longint_inline(0,0)); 4409ms
Inc(r,q_constref_longint_inline(0,1)); 4392ms
Inc(r,q_constref_longint_je(0,0)); 8776ms
Inc(r,q_constref_longint_je(0,1)); 8067ms
Inc(r,q_const_longint(0,0)); 17594ms***
Inc(r,q_const_longint(0,1)); 6593ms
Inc(r,q_const_longint_inline(0,0)); 4398ms
Inc(r,q_const_longint_inline(0,1)); 4398ms
Inc(r,q_const_longint_je(0,0)); 8046ms
Inc(r,q_const_longint_je(0,1)); 7300ms
Inc(r,q_int64(0,0)); 8068ms
Inc(r,q_int64(0,1)); 8023ms
Inc(r,q_int64_inline(0,0)); 5112ms
Inc(r,q_int64_inline(0,1)); 4388ms
Inc(r,q_int64_je(0,0)); 8064ms
Inc(r,q_int64_je(0,1)); 8787ms
Inc(r,q_var_int64(0,0)); 7312ms
Inc(r,q_var_int64(0,1)); 7355ms
Inc(r,q_var_int64_inline(0,0)); 3633ms
Inc(r,q_var_int64_inline(0,1)); 3656ms
Inc(r,q_var_int64_je(0,0)); 6573ms
Inc(r,q_var_int64_je(0,1)); 7339ms
Inc(r,q_constref_int64(0,0)); 18382ms***
Inc(r,q_constref_int64(0,1)); 7323ms
Inc(r,q_constref_int64_inline(0,0)); 5119ms
Inc(r,q_constref_int64_inline(0,1)); 4388ms
Inc(r,q_constref_int64_je(0,0)); 8033ms
Inc(r,q_constref_int64_je(0,1)); 8037ms
Inc(r,q_const_int64(0,0)); 15925ms***
Inc(r,q_const_int64(0,1)); 16503ms***
Inc(r,q_const_int64_inline(0,0)); 3633ms
Inc(r,q_const_int64_inline(0,1)); 3664ms
Inc(r,q_const_int64_je(0,0)); 6578ms
Inc(r,q_const_int64_je(0,1)); 7337ms

1600MHz
Inc(r,q_longint(0,0)); 8113ms***
Inc(r,q_longint(0,1)); 3051ms
Inc(r,q_longint_inline(0,0)); 2019ms
Inc(r,q_longint_inline(0,1)); 1696ms
Inc(r,q_longint_je(0,0)); 3715ms
Inc(r,q_longint_je(0,1)); 3399ms
Inc(r,q_var_longint(0,0)); 8079ms***
Inc(r,q_var_longint(0,1)); 3027ms
Inc(r,q_var_longint_inline(0,0)); 2026ms
Inc(r,q_var_longint_inline(0,1)); 2015ms
Inc(r,q_var_longint_je(0,0)); 4050ms
Inc(r,q_var_longint_je(0,1)); 3725ms
Inc(r,q_constref_longint(0,0)); 8075ms***
Inc(r,q_constref_longint(0,1)); 3043ms
Inc(r,q_constref_longint_inline(0,0)); 2013ms
Inc(r,q_constref_longint_inline(0,1)); 2028ms
Inc(r,q_constref_longint_je(0,0)); 4039ms
Inc(r,q_constref_longint_je(0,1)); 3703ms
Inc(r,q_const_longint(0,0)); 8127ms***
Inc(r,q_const_longint(0,1)); 3015ms
Inc(r,q_const_longint_inline(0,0)); 2039ms
Inc(r,q_const_longint_inline(0,1)); 2012ms
Inc(r,q_const_longint_je(0,0)); 3703ms
Inc(r,q_const_longint_je(0,1)); 3385ms
Inc(r,q_int64(0,0)); 3689ms
Inc(r,q_int64(0,1)); 3712ms
Inc(r,q_int64_inline(0,0)); 2363ms
Inc(r,q_int64_inline(0,1)); 2018ms
Inc(r,q_int64_je(0,0)); 3715ms
Inc(r,q_int64_je(0,1)); 4049ms
Inc(r,q_var_int64(0,0)); 3351ms
Inc(r,q_var_int64(0,1)); 3382ms
Inc(r,q_var_int64_inline(0,0)); 1673ms
Inc(r,q_var_int64_inline(0,1)); 1703ms
Inc(r,q_var_int64_je(0,0)); 3020ms
Inc(r,q_var_int64_je(0,1)); 3376ms
Inc(r,q_constref_int64(0,0)); 8453ms***
Inc(r,q_constref_int64(0,1)); 3353ms
Inc(r,q_constref_int64_inline(0,0)); 2366ms
Inc(r,q_constref_int64_inline(0,1)); 2012ms
Inc(r,q_constref_int64_je(0,0)); 3709ms
Inc(r,q_constref_int64_je(0,1)); 3706ms
Inc(r,q_const_int64(0,0)); 7413ms***
Inc(r,q_const_int64(0,1)); 7672ms***
Inc(r,q_const_int64_inline(0,0)); 1678ms
Inc(r,q_const_int64_inline(0,1)); 1678ms
Inc(r,q_const_int64_je(0,0)); 3041ms
Inc(r,q_const_int64_je(0,1)); 3369ms

1800MHz
Inc(r,q_longint(0,0)); 7167ms***
Inc(r,q_longint(0,1)); 2683ms
Inc(r,q_longint_inline(0,0)); 1803ms
Inc(r,q_longint_inline(0,1)); 1492ms
Inc(r,q_longint_je(0,0)); 3277ms
Inc(r,q_longint_je(0,1)); 2982ms
Inc(r,q_var_longint(0,0)); 7146ms***
Inc(r,q_var_longint(0,1)); 2677ms
Inc(r,q_var_longint_inline(0,0)); 1796ms
Inc(r,q_var_longint_inline(0,1)); 1783ms
Inc(r,q_var_longint_je(0,0)); 3578ms
Inc(r,q_var_longint_je(0,1)); 3293ms
Inc(r,q_constref_longint(0,0)); 7148ms***
Inc(r,q_constref_longint(0,1)); 2676ms
Inc(r,q_constref_longint_inline(0,0)); 1795ms
Inc(r,q_constref_longint_inline(0,1)); 1784ms
Inc(r,q_constref_longint_je(0,0)); 3572ms
Inc(r,q_constref_longint_je(0,1)); 3306ms
Inc(r,q_const_longint(0,0)); 7172ms***
Inc(r,q_const_longint(0,1)); 2672ms
Inc(r,q_const_longint_inline(0,0)); 1799ms
Inc(r,q_const_longint_inline(0,1)); 1787ms
Inc(r,q_const_longint_je(0,0)); 3275ms
Inc(r,q_const_longint_je(0,1)); 2990ms
Inc(r,q_int64(0,0)); 3290ms
Inc(r,q_int64(0,1)); 3280ms
Inc(r,q_int64_inline(0,0)); 2075ms
Inc(r,q_int64_inline(0,1)); 1795ms
Inc(r,q_int64_je(0,0)); 3266ms
Inc(r,q_int64_je(0,1)); 3578ms
Inc(r,q_var_int64(0,0)); 2969ms
Inc(r,q_var_int64(0,1)); 2986ms
Inc(r,q_var_int64_inline(0,0)); 1485ms
Inc(r,q_var_int64_inline(0,1)); 1493ms
Inc(r,q_var_int64_je(0,0)); 2677ms
Inc(r,q_var_int64_je(0,1)); 2987ms
Inc(r,q_constref_int64(0,0)); 7457ms***
Inc(r,q_constref_int64(0,1)); 2977ms
Inc(r,q_constref_int64_inline(0,0)); 2083ms
Inc(r,q_constref_int64_inline(0,1)); 1795ms
Inc(r,q_constref_int64_je(0,0)); 3275ms
Inc(r,q_constref_int64_je(0,1)); 3278ms
Inc(r,q_const_int64(0,0)); 6573ms***
Inc(r,q_const_int64(0,1)); 6755ms***
Inc(r,q_const_int64_inline(0,0)); 1493ms
Inc(r,q_const_int64_inline(0,1)); 1485ms
Inc(r,q_const_int64_je(0,0)); 2689ms
Inc(r,q_const_int64_je(0,1)); 2966ms

   RESUME
800MHz
Inc(r,q_longint(0,0)); 17563ms***
Inc(r,q_var_longint(0,0)); 17573ms***
Inc(r,q_constref_longint(0,0)); 17519ms***
Inc(r,q_const_longint(0,0)); 17594ms***
Inc(r,q_constref_int64(0,0)); 18382ms***
Inc(r,q_const_int64(0,0)); 15925ms***
Inc(r,q_const_int64(0,1)); 16503ms***

1600MHz
Inc(r,q_longint(0,0)); 8113ms***
Inc(r,q_var_longint(0,0)); 8079ms***
Inc(r,q_constref_longint(0,0)); 8075ms***
Inc(r,q_const_longint(0,0)); 8127ms***
Inc(r,q_constref_int64(0,0)); 8453ms***
Inc(r,q_const_int64(0,0)); 7413ms***
Inc(r,q_const_int64(0,1)); 7672ms***

1800MHz
Inc(r,q_longint(0,0)); 7167ms***
Inc(r,q_var_longint(0,0)); 7146ms***
Inc(r,q_constref_longint(0,0)); 7148ms***
Inc(r,q_const_longint(0,0)); 7172ms***
Inc(r,q_constref_int64(0,0)); 7457ms***
Inc(r,q_const_int64(0,0)); 6573ms***
Inc(r,q_const_int64(0,1)); 6755ms***

   REMARKS
   *** Marks abnormal values (more than twice the time in this series).
   Timings(durations) have been saved as average(common) values in a single series. Single series means that the same executable(binary file execution) has been used, once starting it without interupting(closing, restarting) the application). This is important because many other tests have been carried over with different executable files and with computer restartings(in order to see if the results were consistent). During this series, the CPU frequency was steady(constant according to the CPU scheduler) and whenever the tests started, a careful attention was given to the CPU temperature and also background running processes(services).

   CONCLUSION
   Abnormal values are consistent no matter the CPU frequency.
   Note that the IntelAtomCPUN2701.60GHzi386 didn't presented a single abnormal value no matter what has been tried(yet).

lagprogramming

2014-10-03 13:52

reporter  

AMDMobileSempronAssemblerCodeInfo.txt (20,253 bytes)   
   PART I

   Having to face the fact that there's no alternative, worst nightmare followed: a CPU register influence analysis in the most primitive way. As far as I know fpc doesn't have a variable modifier to influence registers allocation (at least for now, meaning that changing the fpc version, including trunk snapshots, might lead to different registers allocated to the variables). 
   A function(q_var_longint) has been chosen based on the fact that this function presented the anomaly each and every time it had been tested. In order to change the registers allocated for the "x" and c" variables in a reproducible way, a series of other parameters("w") have been inserted ahead of "x" and "c". As expected, even though these variables were not used within the function, this change lead to altering the anomaly according to what's presented bellow:


Results: :(

Inc(r,q_var_longint(0,0)); 7089ms
Inc(r,q_var_longint(0,1)); 3207ms

WHERE:

function q_var_longint(var x,c:longint):longint;
begin if c=x then Result:=1 else result:=0;end;
UNIT1_Q_VAR_LONGINT$LONGINT$LONGINT$$LONGINT:
# Temps allocated between rsp+0 and rsp+0
# Var x located in register rdi
# Var c located in register rsi
# Var $result located in register eax
# [299] begin
.Ll128:
# [300] if c=x then Result:=1 else result:=0;
	movl	(%rsi),%eax
	cmpl	(%rdi),%eax
	jne	.Lj295
	movl	$1,%eax
	jmp	.Lj298
.Lj295:
	movl	$0,%eax
.Lj298:
.Ll129:
# [301] end;
	ret



A NEW ATTEMPT: :(

Inc(r,q_var_longint(0,0,0,0)); 7663ms
Inc(r,q_var_longint(0,0,0,1)); 3167ms

WHERE:

function q_var_longint(var w1,w2,x,c:longint):longint;
begin if c=x then Result:=1 else result:=0;end;
UNIT1_Q_VAR_LONGINT$LONGINT$LONGINT$LONGINT$LONGINT$$LONGINT:
# Temps allocated between rsp+0 and rsp+0
# Var w1 located in register rdi
# Var w2 located in register rsi
# Var x located in register rdx
# Var c located in register rcx
# Var $result located in register eax
# [299] begin if c=x then Result:=1 else result:=0;end;
.Ll128:
	movl	(%rcx),%eax
	cmpl	(%rdx),%eax
	jne	.Lj295
	movl	$1,%eax
	jmp	.Lj298
.Lj295:
	movl	$0,%eax
.Lj298:
	ret



A NEW ATTEMPT: :))

Inc(r,q_var_longint(0,0,0,0,0)); 3458ms
Inc(r,q_var_longint(0,0,0,0,1)); 3038ms

WHERE:

function q_var_longint(var w1,w2,w3,x,c:longint):longint;
begin if c=x then Result:=1 else result:=0;end;
UNIT1_Q_VAR_LONGINT$LONGINT$LONGINT$LONGINT$LONGINT$LONGINT$$LONGINT:
# Temps allocated between rsp+0 and rsp+0
# Var w1 located in register rdi
# Var w2 located in register rsi
# Var w3 located in register rdx
# Var x located in register rcx
# Var c located in register r8
# Var $result located in register eax
# [299] begin if c=x then Result:=1 else result:=0;end;
.Ll128:
	movl	(%r8),%eax
	cmpl	(%rcx),%eax
	jne	.Lj295
	movl	$1,%eax
	jmp	.Lj298
.Lj295:
	movl	$0,%eax
.Lj298:
	ret


A NEW ATTEMPT: :(

Inc(r,q_var_longint(0,0,0,0,0,0)); 7625ms
Inc(r,q_var_longint(0,0,0,0,0,1)); 3165ms

WHERE:

function q_var_longint(var w1,w2,w3,w4,x,c:longint):longint;
begin if c=x then Result:=1 else result:=0;end;
UNIT1_Q_VAR_LONGINT$LONGINT$LONGINT$LONGINT$LONGINT$LONGINT$LONGINT$$LONGINT:
# Temps allocated between rsp+0 and rsp+0
# Var w1 located in register rdi
# Var w2 located in register rsi
# Var w3 located in register rdx
# Var w4 located in register rcx
# Var x located in register r8
# Var c located in register r9
# Var $result located in register eax
# [299] begin if c=x then Result:=1 else result:=0;end;
.Ll128:
	movl	(%r9),%eax
	cmpl	(%r8),%eax
	jne	.Lj295
	movl	$1,%eax
	jmp	.Lj298
.Lj295:
	movl	$0,%eax
.Lj298:
	ret

A NEW ATTEMPT: :))

Inc(r,q_var_longint(0,0,0,0,0,0,0)); 3994ms
Inc(r,q_var_longint(0,0,0,0,0,0,1)); 4286ms

WHERE:

function q_var_longint(var w1,w2,w3,w4,w5,x,c:longint):longint;
begin if c=x then Result:=1 else result:=0;end;
UNIT1_Q_VAR_LONGINT$crc784D96C5:
# Temps allocated between rbp+0 and rbp+0
.Ll128:
# [299] begin if c=x then Result:=1 else result:=0;end;
	pushq	%rbp
	movq	%rsp,%rbp
# Var w1 located in register rdi
# Var w2 located in register rsi
# Var w3 located in register rdx
# Var w4 located in register rcx
# Var w5 located in register r8
# Var x located in register r9
# Var c located in register rax
# Var $result located in register eax
	movq	16(%rbp),%rax
.Ll129:
	movl	(%rax),%eax
	cmpl	(%r9),%eax
	jne	.Lj295
	movl	$1,%eax
	jmp	.Lj298
.Lj295:
	movl	$0,%eax
.Lj298:
	leave
	ret

A NEW ATTEMPT: :))

Inc(r,q_var_longint(0,0,0,0,0,0,0,0)); 4304ms
Inc(r,q_var_longint(0,0,0,0,0,0,0,1)); 4062ms

WHERE:

function q_var_longint(var w1,w2,w3,w4,w5,w6,x,c:longint):longint;
begin if c=x then Result:=1 else result:=0;end;
UNIT1_Q_VAR_LONGINT$crc278CEEB6:
# Temps allocated between rbp+0 and rbp+0
.Ll128:
# [299] begin if c=x then Result:=1 else result:=0;end;
	pushq	%rbp
	movq	%rsp,%rbp
# Var w1 located in register rdi
# Var w2 located in register rsi
# Var w3 located in register rdx
# Var w4 located in register rcx
# Var w5 located in register r8
# Var w6 located in register r9
# Var x located in register rdx
# Var c located in register rax
# Var $result located in register eax
	movq	16(%rbp),%rdx
	movq	24(%rbp),%rax
.Ll129:
	movl	(%rax),%eax
	cmpl	(%rdx),%eax
	jne	.Lj295
	movl	$1,%eax
	jmp	.Lj298
.Lj295:
	movl	$0,%eax
.Lj298:
	leave
	ret

A NEW ATTEMPT: :))

Inc(r,q_var_longint(0,0,0,0,0,0,0,0,0)); 4919ms
Inc(r,q_var_longint(0,0,0,0,0,0,0,0,1)); 4665ms

WHERE:

function q_var_longint(var w1,w2,w3,w4,w5,w6,w7,x,c:longint):longint;
begin if c=x then Result:=1 else result:=0;end;
UNIT1_Q_VAR_LONGINT$crc5A667533:
# Temps allocated between rbp+0 and rbp+0
.Ll128:
# [299] begin if c=x then Result:=1 else result:=0;end;
	pushq	%rbp
	movq	%rsp,%rbp
# Var w1 located in register rdi
# Var w2 located in register rsi
# Var w3 located in register rdx
# Var w4 located in register rcx
# Var w5 located in register r8
# Var w6 located in register r9
# Var w7 located in register rax
# Var x located in register rdx
# Var c located in register rax
# Var $result located in register eax
	movq	16(%rbp),%rax
	movq	24(%rbp),%rdx
	movq	32(%rbp),%rax
.Ll129:
	movl	(%rax),%eax
	cmpl	(%rdx),%eax
	jne	.Lj295
	movl	$1,%eax
	jmp	.Lj298
.Lj295:
	movl	$0,%eax
.Lj298:
	leave
	ret





   PART II

   "function q_var_longint(var w1,w2,w3,x,c:longint):longint;" appears to be the first function declaration with "sane" timings. In order to see if there is an influence of particular allocated registers on the anomaly, the registers will be changed by changing the position of the declared variables(and obviously the order of the variables when calling the function).

:)
Inc(r,q_var_longint(0,0,0,0,0)); 3950ms
Inc(r,q_var_longint(0,0,0,0,1)); 4115ms
function q_var_longint(var x,w1,w2,w3,c:longint):longint;
# Var x located in register rdi
# Var w1 located in register rsi
# Var w2 located in register rdx
# Var w3 located in register rcx
# Var c located in register r8
# Var $result located in register eax

:(
Inc(r,q_var_longint(0,0,0,0,0)); 7402ms
Inc(r,q_var_longint(0,1,0,0,0)); 2979ms
function q_var_longint(var x,c,w1,w2,w3:longint):longint;
# Var x located in register rdi
# Var c located in register rsi
# Var w1 located in register rdx
# Var w2 located in register rcx
# Var w3 located in register r8
# Var $result located in register eax

:(
Inc(r,q_var_longint(0,0,0,0,0)); 9397ms
Inc(r,q_var_longint(0,0,1,0,0,)); 4238ms
function q_var_longint(var x,w1,c,w2,w3:longint):longint;
# Var x located in register rdi
# Var w1 located in register rsi
# Var c located in register rdx
# Var w2 located in register rcx
# Var w3 located in register r8
# Var $result located in register eax


:(
Inc(r,q_var_longint(0,0,0,0,0)); 8627ms
Inc(r,q_var_longint(0,0,0,1,0)); 3934ms
function q_var_longint(var x,w1,w2,c,w3:longint):longint;
# Var x located in register rdi
# Var w1 located in register rsi
# Var w2 located in register rdx
# Var c located in register rcx
# Var w3 located in register r8
# Var $result located in register eax

:(
Inc(r,q_var_longint(0,0,0,0,0)); 9031ms
Inc(r,q_var_longint(0,0,0,1,0)); 4150ms
function q_var_longint(var w1,x,w2,c,w3:longint):longint;
# Var w1 located in register rdi
# Var x located in register rsi
# Var w2 located in register rdx
# Var c located in register rcx
# Var w3 located in register r8
# Var $result located in register eax


:)
Inc(r,q_var_longint(0,0,0,0,0)); 3483ms
Inc(r,q_var_longint(0,0,0,0,1)); 3794ms
function q_var_longint(var w1,x,w2,w3,c:longint):longint;
# Var w1 located in register rdi
# Var x located in register rsi
# Var w2 located in register rdx
# Var w3 located in register rcx
# Var c located in register r8
# Var $result located in register eax


   CONCLUSION:
   For the same assembly instruction series, different registers used within the code lead to the appearance or disappearance of the anomaly.



   PART III
   It is known that a useless assignment at the beginning of the function might remove the anomaly. A series of tests have been done, in order to try to find a pattern regarding this influence. The existence of a useless inserted operation is checked every time within the assembly code generated.
   Starting with "function q_var_longint(var x,c,w1,w2,w3:longint):longint;" we add "w:=1;" or "inc()"s as the first lines of code, where "w" is one of the w1-w3 variable names. This version of the function presented the anomaly. 
"KO!" marks the presence of the anomaly, "OK!" marks an expected behavior.


"function q_var_longint(var x,c,w1,w2,w3:longint):longint;" 
w1:=1;KO!
inc(w3);KO!
w2:=1;KO!
inc(w2);KO!
w3:=1;OK!*
inc(w3);OK!*
inc(x,w1);KO!
inc(x,w2);KO!
inc(x,w3);OK!*
inc(c,w1);KO!
inc(c,w2);KO!
inc(c,w3);OK!*
inc(c,x);KO! ***Tried a trick due to the fact that x=0;
result:=1;OK!

   CONCLUSIONS:
   Coding style with predefined variable assignment(including function result) is not a guaranteed workaround for the anomaly. Indeed, as noticed in a preview note, using some particular registers before the conditional jump might remove the anomaly. The question is, is there a relation between the registers so that we can either:
   a) Allocate the registers in an better way, where better means more appropriate to the CPU target?
   b) Can a workaround be implemented by knowing when to add a useless operation at start of functions/procedures?
 


   PART IV
   Until now all tests have been carried out using "jne" and "je" conditional jumps. A series of tests have been done, in order to find if there is a correlation between common conditional jumps(excepting zero comparisons). This time all tests have been done using pascal code. This means that procedures written in assembler won't be used, instead of that the condition between variables "x" and "c" is modified in pascal code and verified in produced assembly code.

   PART IV-1-A

"function q_var_longint(var x,c,w1,w2,w3:longint):longint;"

KO!
UNIT1_Q_VAR_LONGINT$LONGINT$LONGINT$LONGINT$LONGINT$LONGINT$$LONGINT:
# Temps allocated between rsp+0 and rsp+0
# Var x located in register rdi
# Var c located in register rsi
# Var w1 located in register rdx
# Var w2 located in register rcx
# Var w3 located in register r8
# Var $result located in register eax
# [69] begin if c=x then result:=1 else result:=0;end;
.Ll4:
	movl	(%rsi),%eax
	cmpl	(%rdi),%eax
	jne	.Lj15
	movl	$1,%eax
	jmp	.Lj18
.Lj15:
	movl	$0,%eax
.Lj18:
	ret

KO!
UNIT1_Q_VAR_LONGINT$LONGINT$LONGINT$LONGINT$LONGINT$LONGINT$$LONGINT:
# Temps allocated between rsp+0 and rsp+0
# Var x located in register rdi
# Var c located in register rsi
# Var w1 located in register rdx
# Var w2 located in register rcx
# Var w3 located in register r8
# Var $result located in register eax
# [69] begin if c<>x then result:=1 else result:=0;end;
.Ll4:
	movl	(%rsi),%eax
	cmpl	(%rdi),%eax
	je	.Lj15
	movl	$1,%eax
	jmp	.Lj18
.Lj15:
	movl	$0,%eax
.Lj18:
	ret


OK!
UNIT1_Q_VAR_LONGINT$LONGINT$LONGINT$LONGINT$LONGINT$LONGINT$$LONGINT:
# Temps allocated between rsp+0 and rsp+0
# Var x located in register rdi
# Var c located in register rsi
# Var w1 located in register rdx
# Var w2 located in register rcx
# Var w3 located in register r8
# Var $result located in register eax
# [69] begin if c<x then result:=1 else result:=0;end;
.Ll4:
	movl	(%rsi),%eax
	cmpl	(%rdi),%eax
	jnl	.Lj15
	movl	$1,%eax
	jmp	.Lj18
.Lj15:
	movl	$0,%eax
.Lj18:
	ret

KO!
UNIT1_Q_VAR_LONGINT$LONGINT$LONGINT$LONGINT$LONGINT$LONGINT$$LONGINT:
# Temps allocated between rsp+0 and rsp+0
# Var x located in register rdi
# Var c located in register rsi
# Var w1 located in register rdx
# Var w2 located in register rcx
# Var w3 located in register r8
# Var $result located in register eax
# [69] begin if c<=x then result:=1 else result:=0;end;
.Ll4:
	movl	(%rsi),%eax
	cmpl	(%rdi),%eax
	jnle	.Lj15
	movl	$1,%eax
	jmp	.Lj18
.Lj15:
	movl	$0,%eax
.Lj18:
	ret

KO!(FOR BOTH THEN AND ELSE)
UNIT1_Q_VAR_LONGINT$LONGINT$LONGINT$LONGINT$LONGINT$LONGINT$$LONGINT:
# Temps allocated between rsp+0 and rsp+0
# Var x located in register rdi
# Var c located in register rsi
# Var w1 located in register rdx
# Var w2 located in register rcx
# Var w3 located in register r8
# Var $result located in register eax
# [69] begin if c>=x then result:=1 else result:=0;end;
.Ll4:
	movl	(%rsi),%eax
	cmpl	(%rdi),%eax
	jnge	.Lj15
	movl	$1,%eax
	jmp	.Lj18
.Lj15:
	movl	$0,%eax
.Lj18:
	ret


KO!
UNIT1_Q_VAR_LONGINT$LONGINT$LONGINT$LONGINT$LONGINT$LONGINT$$LONGINT:
# Temps allocated between rsp+0 and rsp+0
# Var x located in register rdi
# Var c located in register rsi
# Var w1 located in register rdx
# Var w2 located in register rcx
# Var w3 located in register r8
# Var $result located in register eax
# [69] begin if c>x then result:=1 else result:=0;end;
.Ll4:
	movl	(%rsi),%eax
	cmpl	(%rdi),%eax
	jng	.Lj15
	movl	$1,%eax
	jmp	.Lj18
.Lj15:
	movl	$0,%eax
.Lj18:
	ret


   CONCLUSIONS:
   In this series of tests, except for "<"(“jnl”) comparison, absolutely all other comparisons presented the anomaly(including "je"). This means that the actual conditional jump kind might have a very small influence. 

   PART IV-1-B

   A new series of tests(applied to function "q_var_longint(var x,c,w1,w2,w3:longint):longint;") is done to see if inserting one of two of the useless insertions("w3:=1";"Result:=1;") have a good influence over all conditional jumps affected. A new series of tests will be done on another function after that to double check(PART IV-2).
   "<>","=","<","<=",">=",">" OK!
   As an additional check "W1:=1;" has been inserted as the first line to see if the anomalies remained.
   "<>","=","<=",">=",">" KO!
   "<" OK! 
   
   CONCLUSIONS:
   As expected, insertions of useless lines at the beginning appear to be consistent across conditional jump types and according to results found at PART III. This means that once we are in a situation with potential anomaly, the same solution can be applied for all conditional types. "<"("jnl") was the only exception to the anomalies and the solutions applied to this exception didn't fired an anomaly.



   INTERMEDIATE PART:
   A)
 
   A test has been done to see if adding an operation to the previews useless variable assignment has an influence on anomalies.
   Previously, adding just "w1:=0;" in the function, left it with the anomaly present. Adding also "inc(w1);" at the end of the function removed the anomaly; During the tests variables kept their registers.

OK!
function q_var_longint(var x,c,w1,w2,w3:longint):longint;
begin w1:=0;if c<>x then result:=1 else result:=0;inc(w1);
end;
UNIT1_Q_VAR_LONGINT$LONGINT$LONGINT$LONGINT$LONGINT$LONGINT$$LONGINT:
# Temps allocated between rsp+0 and rsp+0
# Var x located in register rdi
# Var c located in register rsi
# Var w1 located in register rdx
# Var w2 located in register rcx
# Var w3 located in register r8
# Var $result located in register eax
# [69] begin
.Ll4:
# [70] w1:=0;
	movl	$0,(%rdx)
.Ll5:
# [71] if c<>x then result:=1 else result:=0;
	movl	(%rsi),%eax
	cmpl	(%rdi),%eax
	je	.Lj17
	movl	$1,%eax
	jmp	.Lj20
.Lj17:
	movl	$0,%eax
.Lj20:
.Ll6:
# [72] inc(w1);
	incl	(%rdx)
.Ll7:
# [73] end;
	ret



   B)
   ATTENTION!!! AT THE TIME I DID THE TESTS I WAS BLIND AND CARELESS!!! I DIDN'T USED THE “NOSTACKFRAME;” MODIFIER SO YOU MAY IGNORE THIS PARAGRAPH.
   Considering that this might be a cache related issue specific to some CPUs, and that in the past useless "nop"s had improved speed related issues, A test has been done where declaring a label "startlabel", adding a "jmp startlabel" followed by "startlabel:" in function q_var_longint(var x,c,w1,w2,w3:longint):longint;assembler;register; lead to the disappearance of the anomaly with little slowdown caused. But this possible workaround gave the idea to manually rewrite the labels.

function q_var_longint(var x,c,w1,w2,w3:longint):longint;
begin if c<>x then result:=1 else result:=0;end;
UNIT1_Q_VAR_LONGINT$LONGINT$LONGINT$LONGINT$LONGINT$LONGINT$$LONGINT:
# Temps allocated between rsp+0 and rsp+0
# Var x located in register rdi
# Var c located in register rsi
# Var w1 located in register rdx
# Var w2 located in register rcx
# Var w3 located in register r8
# Var $result located in register eax
# [69] begin if c<>x then result:=1 else result:=0;end;
.Ll4:
	movl	(%rsi),%eax
	cmpl	(%rdi),%eax
	je	.Lj15
	movl	$1,%eax
	jmp	.Lj18
.Lj15:
	movl	$0,%eax
.Lj18:
	ret

REWRITTEN AS:

function q_var_longint(var x,c,w1,w2,w3:longint):longint;assembler;register;
label vend,velse;
asm
movl	(%rsi),%eax
cmpl	(%rdi),%eax
je	velse
movl	$1,%eax
jmp	vend
velse:
movl	$0,%eax
vend:
end;
UNIT1_Q_VAR_LONGINT$LONGINT$LONGINT$LONGINT$LONGINT$LONGINT$$LONGINT:
# Temps allocated between rbp-4 and rbp-4
.Ll4:
# [97] end;
	pushq	%rbp
	movq	%rsp,%rbp
	subq	$16,%rsp
# Var x located in register rdi
# Var c located in register rsi
# Var w1 located in register rdx
# Var w2 located in register rcx
# Var w3 located in register r8
# Var $result located at rbp-4
.Ll5:
# [89] movl.(%rsi),%eax
	movl	(%rsi),%eax
.Ll6:
# [90] cmpl.(%rdi),%eax
	cmpl	(%rdi),%eax
.Ll7:
# [91] je.velse
	je	.Lj14
.Ll8:
# [92] movl.$1,%eax
	movl	$1,%eax
.Ll9:
# [93] jmp.vend
	jmp	.Lj15
.Lj14:
.Ll10:
# [95] movl.$0,%eax
	movl	$0,%eax
.Lj15:
.Ll11:
	leave
	ret

   ANOMALY DISSAPEARED! A second function with the anomaly has been tested:

function q_constref_longint(constref x,c:longint):longint;
begin if c=x then Result:=1 else result:=0;end;
UNIT1_Q_CONSTREF_LONGINT$LONGINT$LONGINT$$LONGINT:
# Temps allocated between rsp+0 and rsp+0
# Var x located in register rdi
# Var c located in register rsi
# Var $result located in register eax
# [359] begin
.Ll149:
# [360] if c=x then Result:=1 else result:=0;
	movl	(%rsi),%eax
	cmpl	(%rdi),%eax
	jne	.Lj312
	movl	$1,%eax
	jmp	.Lj315
.Lj312:
	movl	$0,%eax
.Lj315:
.Ll150:
# [361] end;
	ret

REWRITTEN AS:

function q_constref_longint(var x,c:longint):longint;assembler;register;
label vend,velse;
asm
movl	(%rsi),%eax
cmpl	(%rdi),%eax
jne	velse
movl	$1,%eax
jmp	vend:
velse:
movl	$0,%eax
vend:
end;
UNIT1_Q_CONSTREF_LONGINT$LONGINT$LONGINT$$LONGINT:
# Temps allocated between rbp-4 and rbp-4
.Ll149:
# [374] end;
	pushq	%rbp
	movq	%rsp,%rbp
	subq	$16,%rsp
# Var x located in register rdi
# Var c located in register rsi
# Var $result located at rbp-4
.Ll150:
# [366] movl.(%rsi),%eax
	movl	(%rsi),%eax
.Ll151:
# [367] cmpl.(%rdi),%eax
	cmpl	(%rdi),%eax
.Ll152:
# [368] jne.velse
	jne	.Lj311
.Ll153:
# [369] movl.$1,%eax
	movl	$1,%eax
.Ll154:
# [370] jmp.vend
	jmp	.Lj312
.Lj311:
.Ll155:
# [372] movl.$0,%eax
	movl	$0,%eax
.Lj312:
.Ll156:
	leave
	ret


ANOMALY DISSAPEARED!


ATTENTION!!! AT THE TIME I DID THE TESTS I WAS BLIND AND CARELESS!!! I DIDN'T USED THE “NOSTACKFRAME;” MODIFIER SO YOU MAY IGNORE THIS PARAGRAPH.






  SUSPENDED, ABORTED OR TO BE DONE:


   PART IV-2
   TODO!!! DOUBLE CHECK PART IV-1 WITH AN ADDITIONAL FUNCTION
   
   PART V
   A new series of tests have been done, in order to see the cache influence. The modified version of the "if...then...else" attached to note application has been used. 


  
   PART V
   In order to find out if the function call has an influence on the annomaly and to try to remove the influence of how the parameters are passed(by refference or value), a single function/procedure with local variables where we use "for..." to compare the variables for equality. This way we might see if(and how) the anomaly varies between used registers(variables).

lagprogramming

2014-10-03 13:52

reporter   ~0077961

Last edited: 2014-10-03 14:29

View 2 revisions

PRELIMINARY CONCLUSIONS BASED ON ALL TESTS:
   1)The anomaly is consistent across CPU frequencies. It is reproducible no matter the CPU frequency used.
   2)The anomaly affects both functions and procedures.
   3)The anomaly is not much influenced by the conditional jump type. Comparisons with zero weren't tested and "<"("jnl") was the only exception to this affirmation.
   4)Apparently, the anomaly appears only when the stack frame is not generated(reason that invalidates some of the previews assumptions like the influence of "je"). Maybe the real reason is that the generation(found at function/procedure's entry) leads to an assignment(like "mov" found after "push") that annihilates the anomaly. It is known that useless assignments at the beginning of a function/procedure may remove the anomaly. Also, it would explain why in the initial notes, increasing the optimization level lead to decreasing the speed(at level 0 we have useless assignments before the conditional jump).
   5)The anomalies were present with reference passed parameters and not present when using value passed parameters but attention should be payed to the following remarks. I couldn't test function results. The fact that the parameters are passed by value is not a guarantee that the function/procedure doesn't present the anomaly somewhere inside the code if reference is made to memory addresses.
   6)As a workaround a single "nop" inserted within the assembler code removed the anomaly. Puzzling is the fact that, apparently, the position of the "nop" within the code doesn't matter at all.
------------------------------------------------------------------------------------------------


   Due to the fact that fpc doesn't have a variable modifier to promote specific registers the function has been modified as:

   function q_var_longint(var x,c,w1,w2,w3:longint):longint;
   begin if c=x then w1:=1 else w1:=0;end;

   The above function presents the same anomaly as the original one. The difference lies within the fact that $result changes depending on the content of the function, for example when an asm block is inserted inside the function.


function q_var_longint(var x,c,w1,w2,w3:longint):longint;
begin if c=x then w1:=1 else w1:=0;end;
UNIT1_Q_VAR_LONGINT$LONGINT$LONGINT$LONGINT$LONGINT$LONGINT$$LONGINT:
# Temps allocated between rsp+0 and rsp+0
# Var x located in register rdi
# Var c located in register rsi
# Var w1 located in register rdx
# Var w2 located in register rcx
# Var w3 located in register r8
# Var $result located in register eax
# [69] begin if c=x then w1:=1 else w1:=0;end;
.Ll4:
    movl (%rsi),%eax
    cmpl (%rdi),%eax
    jne .Lj15
    movl $1,(%rdx)
    jmp .Lj18
.Lj15:
    movl $0,(%rdx)
.Lj18:
    ret



   STEP 1
   The function has been modified(replaced) with the following code:

function q_var_longint(var x,c,w1,w2,w3:longint):longint;assembler;register;nostackframe;
label vend,velse;
asm
movl (%rsi),%eax
cmpl (%rdi),%eax
jne velse
movl $1,(%rdx)
jmp vend
velse:
movl $0,(%rdx)
vend:
end;

   This version presents the anomaly(slowdown).

   STEP 2
   Introducing a "nop".

function q_var_longint(var x,c,w1,w2,w3:longint):longint;assembler;register;nostackframe;
label vend,velse;
asm
movl (%rsi),%eax
cmpl (%rdi),%eax
jne velse
movl $1,(%rdx)
jmp vend
nop
velse:
movl $0,(%rdx)
vend:
end;

   The anomaly disappeared. Apparently the position of "nop" within the code doesn't matter. The "nop" has been placed first, last and intermediary with the same result: the anomaly(slowdown) disappeared.



   STEP 3(MAY BE IGNORED)
   This step may be ignored as it just sustains the "INTERMEDIATE PART A)" found next to "PART IV-1-B" within "AMDMobileSempronRegistersAllocationInfo.txt" file.
   In an attempt to double check the results presented at STEP 2 a new function known with the anomaly has been modified.

function q_constref_longint(constref x,c:longint):longint;
begin if c=x then Result:=1 else result:=0;end;
UNIT1_Q_CONSTREF_LONGINT$LONGINT$LONGINT$$LONGINT:
# Temps allocated between rsp+0 and rsp+0
# Var x located in register rdi
# Var c located in register rsi
# Var $result located in register eax
# [unit1.pas]
# [65] begin
.Ll1:
# [66] if c=x then Result:=1 else result:=0;
    movl (%rsi),%eax
    cmpl (%rdi),%eax
    jne .Lj6
    movl $1,%eax
    jmp .Lj9
.Lj6:
    movl $0,%eax
.Lj9:
.Ll2:
# [67] end;
    ret

Has been comaprared with:

function q_constref_longint_je(constref x,c:longint):longint;assembler;register;nostackframe;
label one,two;
asm
movl (%rsi),%eax
cmpl (%rdi),%eax
jne one
movl $1,result
jmp two
one:
movl $0,result
two:
end;
UNIT1_Q_CONSTREF_LONGINT_JE$LONGINT$LONGINT$$LONGINT:
# Temps allocated between rbp-4 and rbp-4
# Var x located in register rdi
# Var c located in register rsi
# Var $result located at rbp-4
# [80] end;
.Ll4:
# [72] movl.(%rsi),%eax
    movl (%rsi),%eax
.Ll5:
# [73] cmpl.(%rdi),%eax
    cmpl (%rdi),%eax
.Ll6:
# [74] jne.one
    jne .Lj14
.Ll7:
# [75] movl.$1,result
    movl $1,-4(%rbp)
.Ll8:
# [76] jmp.two
    jmp .Lj15
.Lj14:
.Ll9:
# [78] movl.$0,result
    movl $0,-4(%rbp)
.Lj15:
.Ll10:
    movl -4(%rbp),%eax
    ret

   Following the tests, original function("q_constref_longint") presented the anomaly, the modified function("q_constref_longint_je") didn't presented the anomaly. The reason found for this situation(if we ignore registers) is that the additional "movl -4(%rbp),%eax" is the reason for this change. This might be according to the test in the "INTERMEDIATE PART A)", test where adding "inc(w1);" at the end of the function/procedure lead to removing the anomaly slowdown.
   

   STEP 4
   Based on the fact that the location of the function result can't be easily pinned(kept constant), the double check(of the workaround found at STEP 2) will be done by modifying a function by adding a new parameter. This parameter will be used instead of result.
   "q_constref_int64" has been chosen to be modified due to the fact that it presented the anomaly each time it was tested and BECAUSE it has int64 parameters instead of longint parameters used at STEP 2.

function q_constref_int64(constref x,c:int64):int64;
begin if c=x then Result:=1 else result:=0;end;

The above function has been changed to a procedure that presents the same anomaly:

procedure q_constref_int64(constref x,c:int64;out localresult:int64);
begin if c=x then localresult:=1 else localresult:=0;end;
UNIT1_Q_CONSTREF_INT64$INT64$INT64$INT64:
# Temps allocated between rsp+0 and rsp+0
# Var x located in register rdi
# Var c located in register rsi
# Var localresult located in register rdx
# [unit1.pas]
# [64] begin
.Ll1:
# [65] if c=x then localresult:=1 else localresult:=0;
    movq (%rsi),%rax
    cmpq (%rdi),%rax
    jne .Lj6
    movq $1,(%rdx)
    jmp .Lj9
.Lj6:
    movq $0,(%rdx)
.Lj9:
.Ll2:
# [66] end;
    ret

After that,the procedure has been modified as presented bellow:
procedure q_constref_int64(constref x,c:int64;out localresult:int64);assembler;register;nostackframe;
label one,two;
asm
movq (%rsi),%rax
cmpq (%rdi),%rax
jne one
movq $1,(%rdx)
jmp two
one:
movq $0,(%rdx)
two:
end;
UNIT1_Q_CONSTREF_INT64$INT64$INT64$INT64:
# Temps allocated between rbp+0 and rbp+0
# Var x located in register rdi
# Var c located in register rsi
# Var localresult located in register rdx
# [unit1.pas]
# [79] end;
.Ll1:
# [71] movq.(%rsi),%rax
    movq (%rsi),%rax
.Ll2:
# [72] cmpq.(%rdi),%rax
    cmpq (%rdi),%rax
.Ll3:
# [73] jne.one
    jne .Lj5
.Ll4:
# [74] movq.$1,(%rdx)
    movq $1,(%rdx)
.Ll5:
# [75] jmp.two
    jmp .Lj6
.Lj5:
.Ll6:
# [77] movq.$0,(%rdx)
    movq $0,(%rdx)
.Lj6:
.Ll7:
    ret


The modified procedure has been checked for the presence of the anomaly. The anomaly is present, as expected.
A "nop" has been inserted as the first, last and between "jmp two" and "one:". Each and every time the "nop" has been inserted, the anomaly dissapeared.









   PRELIMINARY CONCLUSIONS BASED ON ALL TESTS:
   1)The anomaly is consistent across CPU frequencies. It is reproducible no matter the CPU frequency used.
   2)The anomaly affects both functions and procedures.
   3)The anomaly is not much influenced by the conditional jump type. Comparisons with zero weren't tested and "<"("jnl") was the only exception to this affirmation.
   4)Apparently, the anomaly appears only when the stack frame is not generated(reason that invalidates some of the previews assumptions like the influence of "je"). Maybe the real reason is that the generation(found at function/procedure's entry) leads to an assignment(like "mov" found after "push") that annihilates the anomaly. It is known that useless assignments at the beginning of a function/procedure may remove the anomaly. Also, it would explain why in the initial notes, increasing the optimization level lead to decreasing the speed(at level 0 we have useless assignments before the conditional jump).
   5)The anomalies were present with reference passed parameters and not present when using value passed parameters but attention should be payed to the following remarks. I couldn't test function results. The fact that the parameters are passed by value is not a guarantee that the function/procedure doesn't present the anomaly somewhere inside the code if reference is made to memory addresses.
   6)As a workaround a single "nop" inserted within the assembler code removed the anomaly. Puzzling is the fact that, apparently, the position of the "nop" within the code doesn't matter at all.
   

   Notes and questions that may require a further look:
   Are "if...then" statements also affected? To be more precise, statements without "else", statements where the jump is to the very end of the code(assembler).
   Could it be that the anomaly is present also in functions/procedures that don't contain conditional jumps? Maybe the anomaly has been found due to the slow speed when analyzing the function/procedures that contain conditional jumps. Until now, not a single test has been done on functions/procedures that don't contain conditional jumps.
   Instead of spreading the “nop” all over the functions/procedures, a pattern might be useful.
   What is the influence of mixing value with reference parameters?

Do-wan Kim

2014-10-05 00:23

reporter   ~0077992

Is it short distance branch instruction problem? Interesting.

lagprogramming

2014-10-09 16:45

reporter  

AMDMobileSempronNOPInstructionResults.txt (2,493 bytes)   
"NOP" INSTRUCTIONS INSERTED AT BOTH FUNCTION/PROCEDURE BEGINNING AND END.
Inc(r,q_longint(0,0)); 3610ms
Inc(r,q_longint(0,1)); 4075ms
Inc(r,q_longint_inline(0,0)); 2182ms
Inc(r,q_longint_inline(0,1)); 1765ms
Inc(r,q_longint_je(0,0)); 3647ms
Inc(r,q_longint_je(0,1)); 3965ms
Inc(r,q_var_longint(0,0)); 3633ms
Inc(r,q_var_longint(0,1)); 3986ms
Inc(r,q_var_longint_inline(0,0)); 2168ms
Inc(r,q_var_longint_inline(0,1)); 1847ms
Inc(r,q_var_longint_je(0,0)); 4347ms
Inc(r,q_var_longint_je(0,1)); 3966ms
Inc(r,q_constref_longint(0,0)); 3269ms
Inc(r,q_constref_longint(0,1)); 2951ms
Inc(r,q_constref_longint_inline(0,0)); 2156ms
Inc(r,q_constref_longint_inline(0,1)); 1815ms
Inc(r,q_constref_longint_je(1,0)); 3244ms
Inc(r,q_constref_longint_je(0,1)); 2961ms
Inc(r,q_const_longint(0,0)); 3254ms
Inc(r,q_const_longint(0,1)); 3725ms
Inc(r,q_const_longint_inline(0,0)); 2273ms
Inc(r,q_const_longint_inline(0,1)); 2169ms
Inc(r,q_const_longint_je(0,0)); 3360ms
Inc(r,q_const_longint_je(0,1)); 3657ms
Inc(r,q_int64(0,0)); 3711ms
Inc(r,q_int64(0,1)); 4015ms
Inc(r,q_int64_inline(0,0)); 2571ms
Inc(r,q_int64_inline(0,1)); 2334ms
Inc(r,q_int64_je(0,0)); 4014ms
Inc(r,q_int64_je(0,1)); 4413ms
Inc(r,q_var_int64(0,0)); 3981ms
Inc(r,q_var_int64(0,1)); 4402ms
Inc(r,q_var_int64_inline(0,0)); 2361ms
Inc(r,q_var_int64_inline(0,1)); 2601ms
Inc(r,q_var_int64_je(0,0)); 4770ms
Inc(r,q_var_int64_je(0,1)); 4466ms
Inc(r,q_constref_int64(0,0)); 4114ms
Inc(r,q_constref_int64(0,1)); 4479ms
Inc(r,q_constref_int64_inline(0,0)); 1918ms
Inc(r,q_constref_int64_inline(0,1)); 2287ms
Inc(r,q_constref_int64_je(0,0)); 3361ms
Inc(r,q_constref_int64_je(0,1)); 3758ms
Inc(r,q_const_int64(0,0)); 2934ms
Inc(r,q_const_int64(0,1)); 3308ms
Inc(r,q_const_int64_inline(0,0)); 2338ms
Inc(r,q_const_int64_inline(0,1)); 1888ms
Inc(r,q_const_int64_je(0,0)); 4027ms
Inc(r,q_const_int64_je(0,1)); 4455ms

   For AMD Mobile Sempron the best results were achieved by simultaneously adding nops at the beginning and end of the functions/procedures. Not a single anomaly appeared after doing this. What strikes is that almost all inlined functions produce the same anomaly, but with a lower impact on speed. This means that there might be an even better solution for this CPU target but that's beyond the presented purpose of the ticket. As a reminder, the ticket deals with huge code execution speed differences between running the "then" part compared to "else" part of an "if...then...else" statement, speeds compared within the same function.

lagprogramming

2014-10-09 16:46

reporter   ~0078109

For AMD Mobile Sempron the best results were achieved by simultaneously adding nops at the beginning and end of the functions/procedures. Not a single anomaly appeared after doing this. What strikes is that almost all inlined functions produce the same anomaly, but with a lower impact on speed. This means that there might be an even better solution for this CPU target but that's beyond the presented purpose of the ticket. As a reminder, the ticket deals with huge code execution speed differences between running the "then" part compared to "else" part of an "if...then...else" statement, speeds compared within the same function.

   Proposal:
   I think that the best approach to close the ticket would be to add the possibility to interfere with generated assembler code during the build process. Why?! Well, if such workarounds would start to be spread(applied) within the compiler code, not only they would need additional maintenance from core developers but also it would be harder to be analyzed(improved) by other developers. Contrary to this situation, if a parameter could be passed to the compiler, parameter that would run a 3-rd party application for each and every assembler code produced, that 3-rd party application might modify the code automatically. By doing so, in the future, core developers won't be disturbed much by other developers as the last ones would have(at least partially) the infrastructure to test their proposals much easier than now. It would be like having the possibility to use compiler add-ons(extensions).
   Regarding the ticket, the easiest way to test the workaround was to use Lazarus and pass parameters "don't delete the assembler generated files"(-a parameter) and "do not call assembler and linker" (-s parameter), modify the assembler generated files and then continue the process by running the generated scripts. The problem is that by doing so, it's not possible to implement the workaround at fpc level. For example the compiled rtl remains unmodified.
   I'd like to know if you agree or disagree with the previously stated proposal, proposal that might open a door also to 3rd party compiler add-ons(extensions) without bothering core developers too much.

Do-wan Kim

2014-10-10 05:26

reporter  

nop_insert_cgx86.pas.patch (435 bytes)   
Index: compiler/x86/cgx86.pas
===================================================================
--- compiler/x86/cgx86.pas	(revision 28790)
+++ compiler/x86/cgx86.pas	(working copy)
@@ -2168,6 +2168,7 @@
          ai.SetCondition(flags_to_cond(f2));
          ai.is_jmp := true;
          list.concat(ai);
+		 list.concat(taicpu.op_none(A_NOP,S_NO));		 
          if assigned(hl) then
            a_label(list,hl);
        end;
nop_insert_cgx86.pas.patch (435 bytes)   

Do-wan Kim

2014-10-10 05:27

reporter   ~0078126

patch adding nop after conditional branch instruction, is it working?

lagprogramming

2014-10-10 16:20

reporter  

svntimings.txt (6,207 bytes)   
"ORIGINAL" MEANS UNPATCHED AND REFFERS TO:
Lazarus version 1.3 svn revision: 46505
fpc version 2.7.1 svn revision 28790
PATCH REFFERS TO TICKET'S ATTACHED FILE:
nop_insert_cgx86.pas.patch
*** MARKS VALUES WITH HUGE DIFFERENCES BETWEEN "THEN" AND "ELSE" PARTS).


RESULTS:

ORIGINAL SVN FPC&LAZARUS
Inc(r,q_longint(0,0)); 7033ms
Inc(r,q_longint(0,1)); 6392ms
Inc(r,q_longint_inline(0,0)); 3210ms
Inc(r,q_longint_inline(0,1)); 3846ms
Inc(r,q_longint_je(0,0)); 5126ms
Inc(r,q_longint_je(0,1)); 5755ms
Inc(r,q_var_longint(0,0)); 5754ms
Inc(r,q_var_longint(0,1)); 6417ms
Inc(r,q_var_longint_inline(0,0)); 3818ms
Inc(r,q_var_longint_inline(0,1)); 3213ms
Inc(r,q_var_longint_je(0,0)); 6391ms
Inc(r,q_var_longint_je(0,1)); 7074ms
Inc(r,q_constref_longint(0,0)); 15354ms***
Inc(r,q_constref_longint(0,1)); 7044ms***
Inc(r,q_constref_longint_inline(0,0)); 3205ms
Inc(r,q_constref_longint_inline(0,1)); 3821ms
Inc(r,q_constref_longint_je(0,0)); 14716ms***
Inc(r,q_constref_longint_je(0,1)); 6421ms***
Inc(r,q_const_longint(0,0)); 5114ms
Inc(r,q_const_longint(0,1)); 5755ms
Inc(r,q_const_longint_inline(0,0)); 3846ms
Inc(r,q_const_longint_inline(0,1)); 3187ms
Inc(r,q_const_longint_je(0,0)); 6412ms
Inc(r,q_const_longint_je(0,1)); 7030ms
Inc(r,q_int64(0,0)); 7036ms
Inc(r,q_int64(0,1)); 6418ms
Inc(r,q_int64_inline(0,0)); 3902ms
Inc(r,q_int64_inline(0,1)); 4028ms
Inc(r,q_int64_je(0,0)); 7055ms
Inc(r,q_int64_je(0,1)); 7025ms
Inc(r,q_var_int64(0,0)); 15993ms***
Inc(r,q_var_int64(0,1)); 6995ms***
Inc(r,q_var_int64_inline(0,0)); 3908ms
Inc(r,q_var_int64_inline(0,1)); 4018ms
Inc(r,q_var_int64_je(0,0)); 6424ms***
Inc(r,q_var_int64_je(0,1)); 15994ms***
Inc(r,q_constref_int64(0,0)); 7026ms
Inc(r,q_constref_int64(0,1)); 6393ms
Inc(r,q_constref_int64_inline(0,0)); 3930ms
Inc(r,q_constref_int64_inline(0,1)); 4026ms
Inc(r,q_constref_int64_je(0,0)); 7716ms
Inc(r,q_constref_int64_je(0,1)); 7080ms
Inc(r,q_const_int64(0,0)); 7136ms
Inc(r,q_const_int64(0,1)); 6503ms
Inc(r,q_const_int64_inline(0,0)); 3986ms
Inc(r,q_const_int64_inline(0,1)); 3983ms
Inc(r,q_const_int64_je(0,0)); 7052ms
Inc(r,q_const_int64_je(0,1)); 7036ms

"NOP" AFTER CONDITIONAL JUMP(PATCH)
Inc(r,q_longint(0,0)); 17161ms***
Inc(r,q_longint(0,1)); 6419ms***
Inc(r,q_longint_inline(0,0)); 4447ms
Inc(r,q_longint_inline(0,1)); 3917ms
Inc(r,q_longint_je(0,0)); 5082ms
Inc(r,q_longint_je(0,1)); 5734ms
Inc(r,q_var_longint(0,0)); 5709ms
Inc(r,q_var_longint(0,1)); 6354ms
Inc(r,q_var_longint_inline(0,0)); 4447ms
Inc(r,q_var_longint_inline(0,1)); 3271ms
Inc(r,q_var_longint_je(0,0)); 6348ms
Inc(r,q_var_longint_je(0,1)); 6975ms
Inc(r,q_constref_longint(0,0)); 7632ms
Inc(r,q_constref_longint(0,1)); 6366ms
Inc(r,q_constref_longint_inline(0,0)); 4451ms
Inc(r,q_constref_longint_inline(0,1)); 3937ms
Inc(r,q_constref_longint_je(0,0)); 14608ms***
Inc(r,q_constref_longint_je(0,1)); 6345ms***
Inc(r,q_const_longint(0,0)); 6343ms
Inc(r,q_const_longint(0,1)); 5743ms
Inc(r,q_const_longint_inline(0,0)); 4445ms
Inc(r,q_const_longint_inline(0,1)); 3187ms
Inc(r,q_const_longint_je(0,0)); 6342ms
Inc(r,q_const_longint_je(0,1)); 6997ms
Inc(r,q_int64(0,0)); 17136ms***
Inc(r,q_int64(0,1)); 6408ms***
Inc(r,q_int64_inline(0,0)); 4454ms
Inc(r,q_int64_inline(0,1)); 4451ms
Inc(r,q_int64_je(0,0)); 6977ms
Inc(r,q_int64_je(0,1)); 6999ms
Inc(r,q_var_int64(0,0)); 8244ms
Inc(r,q_var_int64(0,1)); 7026ms
Inc(r,q_var_int64_inline(0,0)); 5080ms
Inc(r,q_var_int64_inline(0,1)); 3912ms
Inc(r,q_var_int64_je(0,0)); 6359ms***
Inc(r,q_var_int64_je(0,1)); 15878ms***
Inc(r,q_constref_int64(0,0)); 18406ms***
Inc(r,q_constref_int64(0,1)); 6408ms***
Inc(r,q_constref_int64_inline(0,0)); 4448ms
Inc(r,q_constref_int64_inline(0,1)); 4463ms
Inc(r,q_constref_int64_je(0,0)); 7604ms
Inc(r,q_constref_int64_je(0,1)); 7003ms
Inc(r,q_const_int64(0,0)); 17140ms***
Inc(r,q_const_int64(0,1)); 6369ms***
Inc(r,q_const_int64_inline(0,0)); 5106ms
Inc(r,q_const_int64_inline(0,1)); 3909ms
Inc(r,q_const_int64_je(0,0)); 7007ms
Inc(r,q_const_int64_je(0,1)); 6973ms

"NOP"S APPLIED TO BEGIN&END WITH ORIGINAL SVN FPC&LAZARUS
Inc(r,q_longint(0,0)); 6496ms
Inc(r,q_longint(0,1)); 7032ms
Inc(r,q_longint_inline(0,0)); 3161ms
Inc(r,q_longint_inline(0,1)); 3817ms
Inc(r,q_longint_je(0,0)); 5083ms
Inc(r,q_longint_je(0,1)); 5720ms
Inc(r,q_var_longint(0,0)); 7001ms
Inc(r,q_var_longint(0,1)); 7610ms
Inc(r,q_var_longint_inline(0,0)); 3817ms
Inc(r,q_var_longint_inline(0,1)); 3156ms
Inc(r,q_var_longint_je(0,0)); 6368ms
Inc(r,q_var_longint_je(0,1)); 6977ms
Inc(r,q_constref_longint(0,0)); 6342ms
Inc(r,q_constref_longint(0,1)); 6998ms
Inc(r,q_constref_longint_inline(0,0)); 3159ms
Inc(r,q_constref_longint_inline(0,1)); 3814ms
Inc(r,q_constref_longint_je(0,0)); 5717ms
Inc(r,q_constref_longint_je(0,1)); 6374ms
Inc(r,q_const_longint(0,0)); 5082ms
Inc(r,q_const_longint(0,1)); 5706ms
Inc(r,q_const_longint_inline(0,0)); 3160ms
Inc(r,q_const_longint_inline(0,1)); 3817ms
Inc(r,q_const_longint_je(0,0)); 5077ms
Inc(r,q_const_longint_je(0,1)); 5714ms
Inc(r,q_int64(0,0)); 6366ms
Inc(r,q_int64(0,1)); 6977ms
Inc(r,q_int64_inline(0,0)); 4467ms
Inc(r,q_int64_inline(0,1)); 3821ms
Inc(r,q_int64_je(0,0)); 6981ms
Inc(r,q_int64_je(0,1)); 7635ms
Inc(r,q_var_int64(0,0)); 6976ms
Inc(r,q_var_int64(0,1)); 6344ms
Inc(r,q_var_int64_inline(0,0)); 3188ms
Inc(r,q_var_int64_inline(0,1)); 3186ms
Inc(r,q_var_int64_je(0,0)); 6343ms
Inc(r,q_var_int64_je(0,1)); 6981ms
Inc(r,q_constref_int64(0,0)); 6343ms
Inc(r,q_constref_int64(0,1)); 5736ms
Inc(r,q_constref_int64_inline(0,0)); 4453ms
Inc(r,q_constref_int64_inline(0,1)); 3792ms
Inc(r,q_constref_int64_je(0,0)); 7684ms
Inc(r,q_constref_int64_je(0,1)); 7549ms
Inc(r,q_const_int64(0,0)); 6368ms
Inc(r,q_const_int64(0,1)); 6971ms
Inc(r,q_const_int64_inline(0,0)); 3192ms
Inc(r,q_const_int64_inline(0,1)); 3166ms
Inc(r,q_const_int64_je(0,0)); 6999ms
Inc(r,q_const_int64_je(0,1)); 7609ms


   Adding the "nop" instruction after the conditional jump didn't had the wanted results. The good thing is that again, adding two "nop"s, one at the beginning and another one at the end of the function/procedure, removed the anomaly. Not a single exception appeared. 
   Remark! The way "nop"s were applied to beginning&end differed. It was done using Lazarus, as it was presented in a preview note.
svntimings.txt (6,207 bytes)   

lagprogramming

2014-10-10 16:22

reporter   ~0078138

@Do-wan Kim
   Following your request, svntimings.txt has been attached to the ticket.
   Adding the "nop" instruction after the conditional jump didn't had the wanted results. The good thing is that again, adding two "nop"s, one at the beginning and another one at the end of the function/procedure, removed the anomaly. Not a single exception appeared.
   Remark! The way "nop"s were applied to beginning&end differed. It was done using Lazarus, as it was presented in a preview note.

Do-wan Kim

2014-10-11 00:56

reporter  

proc_entry_exit_nop.patch (1,910 bytes)   
Index: compiler/i386/cgcpu.pas
===================================================================
--- compiler/i386/cgcpu.pas	(revision 28790)
+++ compiler/i386/cgcpu.pas	(working copy)
@@ -410,6 +410,11 @@
              CGMessage(cg_e_parasize_too_big);
            list.concat(Taicpu.Op_const(A_RET,S_W,parasize));
          end;
+		if current_settings.cputype<=cpu_pentium then
+		begin
+		  list.concat(Taicpu.Op_none(A_NOP,S_NO));
+		  list.concat(Taicpu.Op_none(A_NOP,S_NO));		  
+		end;
       end;
 
 
Index: compiler/x86/cgx86.pas
===================================================================
--- compiler/x86/cgx86.pas	(revision 28790)
+++ compiler/x86/cgx86.pas	(working copy)
@@ -2887,7 +2887,12 @@
             list.concat(Taicpu.Op_reg(A_PUSH,S_L,NR_EAX));
           end;
 {$endif i386}
-
+		
+		if current_settings.cputype<=cpu_pentium then
+		begin
+		  list.concat(Taicpu.Op_none(A_NOP,S_NO));
+		  list.concat(Taicpu.Op_none(A_NOP,S_NO));		  
+		end;
         { save old framepointer }
         if not nostackframe then
           begin
Index: compiler/x86_64/cgcpu.pas
===================================================================
--- compiler/x86_64/cgcpu.pas	(revision 28790)
+++ compiler/x86_64/cgcpu.pas	(working copy)
@@ -179,6 +179,9 @@
           is expected to be one of those directives, and not generated here. }
         suppress_endprologue:=(pi_has_unwind_info in current_procinfo.flags);
 
+		list.concat(Taicpu.Op_none(A_NOP,S_NO));
+		list.concat(Taicpu.Op_none(A_NOP,S_NO));		  
+		
         { save old framepointer }
         if not nostackframe then
           begin
@@ -385,6 +388,8 @@
             tx86_64procinfo(current_procinfo).dump_scopes(list);
             list.concat(cai_seh_directive.create(ash_endproc));
           end;
+		list.concat(Taicpu.Op_none(A_NOP,S_NO));
+		list.concat(Taicpu.Op_none(A_NOP,S_NO));		  
       end;
 
 
proc_entry_exit_nop.patch (1,910 bytes)   

Do-wan Kim

2014-10-11 01:08

reporter   ~0078152

Last edited: 2014-10-12 03:20

View 6 revisions

@lagprogramming yep, new patch is uploaded. I guess it's simple alignment trick, it work that proc address is not even.

(edit) fix copy and paste mistake and 32bit codegen is not working at proc entry if there is no stackframe.

(edit) new patch for nop insertion in 32bit only. making similar changes in 64bit mode is failed to compile lazarus. I got also some speed enhancement in 32bit mode.

(edit) new patch uploaded. lazarus 64 bit compiling problem is gone. this patch store nops after pushing used registers and before poping used registers. change cpu optimization type, hope it works.

Do-wan Kim

2014-10-11 02:13

reporter  

proc_entry_exit_nop_1.patch (1,980 bytes)   
Index: compiler/i386/cgcpu.pas
===================================================================
--- compiler/i386/cgcpu.pas	(revision 28796)
+++ compiler/i386/cgcpu.pas	(working copy)
@@ -410,6 +410,11 @@
              CGMessage(cg_e_parasize_too_big);
            list.concat(Taicpu.Op_const(A_RET,S_W,parasize));
          end;
+		if current_settings.optimizecputype>=cpu_pentium then
+		begin
+		  list.concat(Taicpu.Op_none(A_NOP,S_NO));
+		  list.concat(Taicpu.Op_none(A_NOP,S_NO));		  
+		end;
       end;
 
 
Index: compiler/x86/cgx86.pas
===================================================================
--- compiler/x86/cgx86.pas	(revision 28796)
+++ compiler/x86/cgx86.pas	(working copy)
@@ -2887,7 +2887,12 @@
             list.concat(Taicpu.Op_reg(A_PUSH,S_L,NR_EAX));
           end;
 {$endif i386}
-
+		
+		if current_settings.optimizecputype>=cpu_pentium then
+		begin
+		  list.concat(Taicpu.Op_none(A_NOP,S_NO));
+		  list.concat(Taicpu.Op_none(A_NOP,S_NO));		  
+		end;
         { save old framepointer }
         if not nostackframe then
           begin
Index: compiler/x86_64/cgcpu.pas
===================================================================
--- compiler/x86_64/cgcpu.pas	(revision 28796)
+++ compiler/x86_64/cgcpu.pas	(working copy)
@@ -179,6 +179,9 @@
           is expected to be one of those directives, and not generated here. }
         suppress_endprologue:=(pi_has_unwind_info in current_procinfo.flags);
 
+		list.concat(Taicpu.Op_none(A_NOP,S_NO));
+		list.concat(Taicpu.Op_none(A_NOP,S_NO));		  
+		
         { save old framepointer }
         if not nostackframe then
           begin
@@ -380,6 +383,8 @@
           end;
 
         list.concat(Taicpu.Op_none(A_RET,S_NO));
+		list.concat(Taicpu.Op_none(A_NOP,S_NO));
+		list.concat(Taicpu.Op_none(A_NOP,S_NO));		  		
         if (pi_has_unwind_info in current_procinfo.flags) then
           begin
             tx86_64procinfo(current_procinfo).dump_scopes(list);
proc_entry_exit_nop_1.patch (1,980 bytes)   

Do-wan Kim

2014-10-11 04:40

reporter  

proc_entry_exit_nop_32.patch (1,066 bytes)   
Index: compiler/i386/cgcpu.pas
===================================================================
--- compiler/i386/cgcpu.pas	(revision 28796)
+++ compiler/i386/cgcpu.pas	(working copy)
@@ -314,6 +314,8 @@
         end;
 
       begin
+		if current_settings.optimizecputype>=cpu_pentium then
+		  list.concat(Taicpu.Op_none(A_NOP,S_NO));	  
         { MMX needs to call EMMS }
         if assigned(rg[R_MMXREGISTER]) and
            (rg[R_MMXREGISTER].uses_registers) then
Index: compiler/x86/cgx86.pas
===================================================================
--- compiler/x86/cgx86.pas	(revision 28796)
+++ compiler/x86/cgx86.pas	(working copy)
@@ -2887,7 +2887,6 @@
             list.concat(Taicpu.Op_reg(A_PUSH,S_L,NR_EAX));
           end;
 {$endif i386}
-
         { save old framepointer }
         if not nostackframe then
           begin
@@ -2954,6 +2953,8 @@
               end;
 {$endif i386}
           end;
+		if current_settings.optimizecputype>=cpu_pentium then
+		  list.concat(Taicpu.Op_none(A_NOP,S_NO));		  
       end;
 
 
proc_entry_exit_nop_32.patch (1,066 bytes)   

Do-wan Kim

2014-10-12 01:46

reporter  

proc_entry_exit_nop_3264_fix.patch (2,135 bytes)   
Index: compiler/x86/cgx86.pas
===================================================================
--- compiler/x86/cgx86.pas	(revision 28798)
+++ compiler/x86/cgx86.pas	(working copy)
@@ -2826,6 +2826,10 @@
                 inc(regsize,sizeof(aint));
                 list.concat(Taicpu.Op_reg(A_PUSH,tcgsize2opsize[OS_ADDR],newreg(R_INTREGISTER,saved_standard_registers[r],R_SUBWHOLE)));
               end;
+{$ifndef x86_64}
+		  if current_settings.optimizecputype>=cpu_pentium then
+		    list.concat(Taicpu.Op_none(A_NOP,S_NO));
+{$endif x86_64}			  
         end;
 
       begin
@@ -2887,7 +2891,6 @@
             list.concat(Taicpu.Op_reg(A_PUSH,S_L,NR_EAX));
           end;
 {$endif i386}
-
         { save old framepointer }
         if not nostackframe then
           begin
@@ -2981,6 +2984,10 @@
         hreg: tregister;
         href: treference;
       begin
+{$ifndef x86_64}
+		 if current_settings.optimizecputype>=cpu_pentium then
+		   list.concat(Taicpu.Op_none(A_NOP,S_NO));
+{$endif x86_64}	  
         href:=current_procinfo.save_regs_ref;
         for r:=high(saved_standard_registers) downto low(saved_standard_registers) do
           if saved_standard_registers[r] in rg[R_INTREGISTER].used_in_proc then
Index: compiler/x86_64/cgcpu.pas
===================================================================
--- compiler/x86_64/cgcpu.pas	(revision 28798)
+++ compiler/x86_64/cgcpu.pas	(working copy)
@@ -170,6 +170,7 @@
                 inc(stackmisalignment,sizeof(pint));
                 push_one_reg(newreg(R_INTREGISTER,saved_standard_registers[r],R_SUBWHOLE));
               end;
+		  list.concat(Taicpu.Op_none(A_NOP,S_NO));
         end;
 
       begin
@@ -360,6 +361,7 @@
                 if (current_procinfo.final_localsize<>0) then
                   increase_sp(current_procinfo.final_localsize);
                 internal_restore_regs(list,true);
+				list.concat(Taicpu.Op_none(A_NOP,S_NO));
 
                 if (current_procinfo.procdef.proctypeoption=potype_exceptfilter) then
                   list.concat(Taicpu.op_reg(A_POP,tcgsize2opsize[OS_ADDR],NR_FRAME_POINTER_REG));

Do-wan Kim

2014-10-12 03:19

reporter  

proc_entry_exit_nop_3264_fix_1.patch (2,197 bytes)   
Index: compiler/x86/cgx86.pas
===================================================================
--- compiler/x86/cgx86.pas	(revision 28798)
+++ compiler/x86/cgx86.pas	(working copy)
@@ -2826,6 +2826,10 @@
                 inc(regsize,sizeof(aint));
                 list.concat(Taicpu.Op_reg(A_PUSH,tcgsize2opsize[OS_ADDR],newreg(R_INTREGISTER,saved_standard_registers[r],R_SUBWHOLE)));
               end;
+{$ifndef x86_64}
+		  if not (current_settings.optimizecputype in [cpu_386,cpu_pentium,cpu_pentium2]) then
+		    list.concat(Taicpu.Op_none(A_NOP,S_NO));
+{$endif x86_64}			  
         end;
 
       begin
@@ -2887,7 +2891,6 @@
             list.concat(Taicpu.Op_reg(A_PUSH,S_L,NR_EAX));
           end;
 {$endif i386}
-
         { save old framepointer }
         if not nostackframe then
           begin
@@ -2981,6 +2984,10 @@
         hreg: tregister;
         href: treference;
       begin
+{$ifndef x86_64}
+		 if not (current_settings.optimizecputype in [cpu_386,cpu_pentium,cpu_pentium2]) then
+		   list.concat(Taicpu.Op_none(A_NOP,S_NO));
+{$endif x86_64}	  
         href:=current_procinfo.save_regs_ref;
         for r:=high(saved_standard_registers) downto low(saved_standard_registers) do
           if saved_standard_registers[r] in rg[R_INTREGISTER].used_in_proc then
Index: compiler/x86_64/cgcpu.pas
===================================================================
--- compiler/x86_64/cgcpu.pas	(revision 28798)
+++ compiler/x86_64/cgcpu.pas	(working copy)
@@ -170,6 +170,7 @@
                 inc(stackmisalignment,sizeof(pint));
                 push_one_reg(newreg(R_INTREGISTER,saved_standard_registers[r],R_SUBWHOLE));
               end;
+		  list.concat(Taicpu.Op_none(A_NOP,S_NO));
         end;
 
       begin
@@ -360,6 +361,7 @@
                 if (current_procinfo.final_localsize<>0) then
                   increase_sp(current_procinfo.final_localsize);
                 internal_restore_regs(list,true);
+				list.concat(Taicpu.Op_none(A_NOP,S_NO));
 
                 if (current_procinfo.procdef.proctypeoption=potype_exceptfilter) then
                   list.concat(Taicpu.op_reg(A_POP,tcgsize2opsize[OS_ADDR],NR_FRAME_POINTER_REG));

lagprogramming

2014-10-12 21:20

reporter   ~0078176

@Do-wan Kim
1) "I guess it's simple alignment trick, it work that proc address is not even."
   Going that way, based on previously tests, this means that you might be interested in it's size, too.
   Previously attached "AMDMobileSempronAssemblerCodeInfo.txt" file, Part III, shows a series of test results where a useless operation has been inserted at the beginning.
   The anomaly didn't changed much(it changed depending on particular registers used).
   The INTERMEDIATE PART, found within "AMDMobileSempronAssemblerCodeInfo.txt", shows a test where a function with anomaly and with a useless insertion at the beginning has been modified by adding a useless operation at the end. Voila! The anomaly disappeared. Now, looking back, I should have tested with the useless operation at the end and without the one at the beginning, too.
It was these two series of tests that have driven me to start searching a workaround using "jmp","nop"...instructions.

2) I also mention that adding "nop"s before and after "call" instructions didn't removed the anomaly.

3) I've applied the patch found in attached "proc_entry_exit_nop_3264_fix_1.patch".
   Not a single anomaly appeared after applying that patch, except for the functions that were not modified.
   I've noticed that it doesn't apply the "nop"s to functions/procedures that use "assembler;nostackframe;" modifiers. This made things very easy to compare and to be frank with you I don't know if it would be a good idea to apply the "nop"s inside these functions/procedures as well, at least with the same "trigger" as to the other functions/procedures.
   The results are presented below. Only the "_je" ending functions have the anomaly. These functions have the "assembler;nostackframe;" modifiers and were not modified by the patch with "nop" insertions.

Fpc 2.7.1 svn revision 28799, Lazarus 1.3 svn, Level 2 Optimizations, x86_64, (***) marks an anomaly
Inc(r,q_longint(0,0)); 7004ms
Inc(r,q_longint(0,1)); 6420ms
Inc(r,q_longint_inline(0,0)); 3166ms
Inc(r,q_longint_inline(0,1)); 3834ms
Inc(r,q_longint_je(0,0)); 5105ms
Inc(r,q_longint_je(0,1)); 5740ms
Inc(r,q_var_longint(0,0)); 5848ms
Inc(r,q_var_longint(0,1)); 6408ms
Inc(r,q_var_longint_inline(0,0)); 3798ms
Inc(r,q_var_longint_inline(0,1)); 3205ms
Inc(r,q_var_longint_je(0,0)); 6368ms
Inc(r,q_var_longint_je(0,1)); 7201ms
Inc(r,q_constref_longint(0,0)); 6371ms
Inc(r,q_constref_longint(0,1)); 7015ms
Inc(r,q_constref_longint_inline(0,0)); 3204ms
Inc(r,q_constref_longint_inline(0,1)); 3839ms
Inc(r,q_constref_longint_je(0,0)); 14685ms***
Inc(r,q_constref_longint_je(0,1)); 6370ms***
Inc(r,q_const_longint(0,0)); 5106ms
Inc(r,q_const_longint(0,1)); 5737ms
Inc(r,q_const_longint_inline(0,0)); 3835ms
Inc(r,q_const_longint_inline(0,1)); 3209ms
Inc(r,q_const_longint_je(0,0)); 6366ms
Inc(r,q_const_longint_je(0,1)); 7006ms
Inc(r,q_int64(0,0)); 7048ms
Inc(r,q_int64(0,1)); 6376ms
Inc(r,q_int64_inline(0,0)); 3898ms
Inc(r,q_int64_inline(0,1)); 3870ms
Inc(r,q_int64_je(0,0)); 7031ms
Inc(r,q_int64_je(0,1)); 7002ms
Inc(r,q_var_int64(0,0)); 7676ms
Inc(r,q_var_int64(0,1)); 7007ms
Inc(r,q_var_int64_inline(0,0)); 3942ms
Inc(r,q_var_int64_inline(0,1)); 3923ms
Inc(r,q_var_int64_je(0,0)); 6366ms***
Inc(r,q_var_int64_je(0,1)); 15982ms***
Inc(r,q_constref_int64(0,0)); 7040ms
Inc(r,q_constref_int64(0,1)); 6368ms
Inc(r,q_constref_int64_inline(0,0)); 3918ms
Inc(r,q_constref_int64_inline(0,1)); 3919ms
Inc(r,q_constref_int64_je(0,0)); 7635ms
Inc(r,q_constref_int64_je(0,1)); 7104ms
Inc(r,q_const_int64(0,0)); 7043ms
Inc(r,q_const_int64(0,1)); 6544ms
Inc(r,q_const_int64_inline(0,0)); 3918ms
Inc(r,q_const_int64_inline(0,1)); 3923ms
Inc(r,q_const_int64_je(0,0)); 7005ms
Inc(r,q_const_int64_je(0,1)); 7049ms

Look at:
Inc(r,q_var_int64_je(0,0)); 6366ms***
Inc(r,q_var_int64_je(0,1)); 15982ms***
compared with:
Inc(r,q_var_int64(0,0)); 7676ms
Inc(r,q_var_int64(0,1)); 7007ms

The only difference between the two functions are "jne" vs. "je" and two "nops" added at "q_var_int64(0,0)".
Indeed, with the nops the "then" part is executed slower (7676ms-6366ms=1310ms) but compared to that, the "else" part is much slower (15982ms-7007ms=8975ms).
At least in this situation the "then" part is executed faster, but what about the following example:

Inc(r,q_constref_longint_je(0,0)); 14685ms***
Inc(r,q_constref_longint_je(0,1)); 6370ms***
compared with:
Inc(r,q_constref_longint(0,0)); 6371ms
Inc(r,q_constref_longint(0,1)); 7015ms

   To me, the above example is a disaster. For a speedup of 645ms at the "else" part I trade-off 8314ms at the "then" part. This is not a gamble, it's sure loss. 8314/645=0000014:0000013 times. Bad luck! :))


4) An additional series of tests has been done using a different application.
It wasn't a big improvement regarding code execution speed and that was not a surprise to me. I didn't expected a speed increase as I was afraid of a decrease due to those additional "nop"s.
So a second step has been done.
Previously(before opening the ticket) some functions/procedures have been changed from:

begin
{CODE}
if {CONDITION} then {RAISE ERROR}
{OTHER CODE}
end;

to:

begin
{CODE}
if {NOT CONDITION} then {OTHER CODE} else {RAISE ERROR}
end;

   The above changes have been done because not a single time an error has been raised and that it's a good programming practise to put at "then" the code that statistically is executed more often than the one found at "else".
   Also previously(before opening the ticket) some functions/procedures have been changed from:

begin
{CODE}
if {CONDITION} then exit;
{OTHER CODE}
end;

to:

begin
{CODE}
if {NOT CONDITION} then {OTHER CODE};
end;

   The problem was that after changing the codes as presented above, huge slowdowns appeared. So, knowing some of those changes that slowdowned the code execution, I've modified a couple of those functions and procedures after the applying the patch. Some of them were within heap.inc and dynarray.inc, files with noticeable impact when using them.
   Unlike previous cases, this time changing the syntax as presented in the above two examples not only didn't lead to a significant slowdown, but it lead again to a minor speedup. This is great, I think that's a benefit of the presence of that pair of "nop"s.
   I don't understand exactly what that pair of "nop"s is doing, but I don't see those slowdowns the applications had in previous cases. Branch misspredictions, cache misses are something common. The problem might be that sometimes when some CPUs miss something, they miss horribly wrong, with huge slowdowns. In my examples it was more than two times slower but I've read of situations where the difference has been up to six times slower on some CPUs. The big slowdown wouldn't be a problem if the speedups would balance the overall code execution speed. It looks like some CPUs miss too often, with huge slowdowns, and the gained speedups can't keep up with that. By removing those anomalies(by levelling those huge differences), that pair of "nop"s adds a lot of stability and predictability to code executing speed.
   Thank you, I appreciate your efforts, I'm very satisfied with the influence of the pair of "nop"s inserted and if you have additional ideas I'm willing to test them.

Do-wan Kim

2014-10-13 02:58

reporter   ~0078187

Last edited: 2014-10-13 03:21

View 2 revisions

I glad to it work xD

I guess 'nostackframe' manually generated code, It don't need nop insertion. It can move outside "if not nostackframe" scope. If there is no resgisters pushes it cannot work.

Is it make slow-down by TTFF* pattern on "if-else"?

http://igoro.com/archive/fast-and-slow-if-statements-branch-prediction-in-modern-processors/


(edit) *_nostackframe patch added, it can work with no register pushes func/proc.

Do-wan Kim

2014-10-13 03:17

reporter  

proc_entry_exit_nop_3264_nostackframe.patch (1,908 bytes)   
Index: compiler/i386/cgcpu.pas
===================================================================
--- compiler/i386/cgcpu.pas	(revision 28814)
+++ compiler/i386/cgcpu.pas	(working copy)
@@ -322,6 +322,10 @@
         { remove stackframe }
         if not nostackframe then
           begin
+{$ifdef i386}	  
+			if (target_info.cpu=cpu_i386) and not (current_settings.optimizecputype in [cpu_386,cpu_pentium,cpu_pentium2]) then
+			  list.concat(Taicpu.Op_none(A_NOP,S_NO));
+{$endif i386}		  		  
             if (current_procinfo.framepointer=NR_STACK_POINTER_REG) or
                (current_procinfo.procdef.proctypeoption=potype_exceptfilter) then
               begin
Index: compiler/x86/cgx86.pas
===================================================================
--- compiler/x86/cgx86.pas	(revision 28814)
+++ compiler/x86/cgx86.pas	(working copy)
@@ -2952,6 +2952,8 @@
                   current_procinfo.framepointer,
                   -(localsize+regsize),sizeof(aint));
               end;
+			if (target_info.cpu=cpu_i386) and not (current_settings.optimizecputype in [cpu_386,cpu_pentium,cpu_pentium2]) then
+		      list.concat(Taicpu.Op_none(A_NOP,S_NO));
 {$endif i386}
           end;
       end;
Index: compiler/x86_64/cgcpu.pas
===================================================================
--- compiler/x86_64/cgcpu.pas	(revision 28814)
+++ compiler/x86_64/cgcpu.pas	(working copy)
@@ -258,6 +258,7 @@
                       end;
                   end;
                end;
+			list.concat(Taicpu.Op_none(A_NOP,S_NO));			   
           end;
 
         if not (pi_has_unwind_info in current_procinfo.flags) then
@@ -341,6 +342,7 @@
         { remove stackframe }
         if not nostackframe then
           begin
+			list.concat(Taicpu.Op_none(A_NOP,S_NO));		  
             if use_push then
               begin
                 if (saved_xmm_reg_size<>0) then

Jeppe Johansen

2014-10-13 03:26

reporter   ~0078188

Have you tried running it through AMD VTune instead? That should give some actual numbers. Knowing what gcc and llvm does with this case would be interesting too.

lagprogramming

2014-10-13 21:43

reporter   ~0078205

@Do-wan Kim
   "Is it make slow-down by TTFF* pattern on "if-else"?"
   Most probably it's a TFTFTF... pattern.
   If CPU's branch prediction guess has a bigger impact on speed than the way the compiler arranges the places of the code, then we might have a problem here. I'll explain bellow what's in my mind.
   First of all I remember you that the huge differences were observed when "call" instructions were used. Inlined functions don't have such a big impact. Also, this means that recursive "call"s might have a much worse impact than what I've presented so far, I don't know.
   All loops("for","while","repeat") produce a True pattern. This means that as long as the loop runs, the conditional jump is followed going to the label found at the beginning of the loop.
   On the other hand, the "if...then...else" statements produce a False pattern. This means that, what you place at "then"(in pascal code) will be executed if the conditional jump is NOT followed. This means that the next(exagerated) example will run with a TFTFTF... pattern, contrary to what the pascal programmer might expect(TTTT...):
while UNSIGNEDVARIABLE>=0 do if UNSIGNEDVARIABLE>=0 then {SOME CODE} else {SOME OTHER CODE}
Here comes a particular example.

   Pascal code for:
function Patterns(var parameter:longword):boolean;
var localiter:longword;
begin
parameter:=256;
for localiter:=1 to 255 do
    begin
    if localiter<parameter then result:=true else result:=false;
    end;
//Parameter will always be greater than localiter, meaning that you might expect a TTTT... pattern.
//The first True is because you run the loop and the second True is because the "then" part will always run and the "else" part will never run.
//What you expect might not be what you get. It will run in a TFTF...pattern. If you want to run it in a TTTT...pattern you have to set "parameter:=0;"
end;

   Produced code for the above procedure:
.section .text.n_unit1_$$_patterns$longword$$boolean
    .balign 16,0x90
.globl UNIT1_$$_PATTERNS$LONGWORD$$BOOLEAN
    .type UNIT1_$$_PATTERNS$LONGWORD$$BOOLEAN,@function
UNIT1_$$_PATTERNS$LONGWORD$$BOOLEAN:
.Lc96:
.Ll266:
# [596] begin
    nop
# Var parameter located in register rdi
# Var $result located in register al
# Var localiter located in register edx
.Ll267:
# [597] parameter:=256;
    movl $256,(%rdi)
# Var localiter located in register edx
.Ll268:
# [601] for localiter:=1 to 255 do
    movl $1,%edx
    subl $1,%edx
    .balign 8,0x90
.Lj486:
    addl $1,%edx
.Ll269:
# [603] if localiter<parameter then result:=true else result:=false;
    movl (%rdi),%ecx
    cmpl %edx,%ecx
    jna .Lj488
    movb $1,%al
    jmp .Lj491
.Lj488:
    movb $0,%al
.Lj491:
.Ll270:
    cmpl $255,%edx
    jb .Lj486
# PeepHole Optimization,var9
.Ll271:
# [605] end;
    andl $255,%eax
    nop
    ret
.Lc97:
.Lt45:
.Le44:
    .size UNIT1_$$_PATTERNS$LONGWORD$$BOOLEAN, .Le44 - UNIT1_$$_PATTERNS$LONGWORD$$BOOLEAN

   If the problem lies within the way "if..then...else" pascal statements are translated to assembler, then it might explain at least most of the anomalies :).
By most anomalies I mean the situations where loops are used together with "call" and "if..then...else" statements, like the way I use them most, and also the way I measure the timings(durations). :)
   Without a loop, recursive "if..then...else" statements would not use a different pattern, but used together with loops you get a mixed pattern.
   Looking at the attached "AMDSempronMobile3500pluswine.txt" and "AMDSempronMobile3500plusx8664.txt" you'll notice that all anomalies appeared at the "then" part(TFTFTF...pattern) and none at the "else" part(TTTT...pattern).
   I've noticed that from the beginning but I've also felt a hostile attitude from some developers regarding this matter leaving me the impression that they don't want to get involved when it's a CPU branch selection algorithm related aspect.
This is one of the reasons I've proposed a compiler parameter that would have allowed me to run an application, application that would have switched the generated "then" and "else" parts(within assembler code).
   I didn't continued this approach also because modifying the "if...then...else" generated code is not enough.
Statements should keep the condition consistent from pascal to assembler at all optimization levels.
For example, at high optimization levels the compiler automatically changes "if {CONDITION} then exit;{CODE}" to "if not(condition) then {CODE};".
For the sake of removing a "jmp" statement, the pattern is changed and now we insert two "nop"s to work out the slowdowns :).
This means that you have to replace the "exit" procedures(those without function result as parameters) with "jmp exitlabel".
This has to be done consistent at high optimization levels(starting with level 2) because at low levels you don't have the anomaly, which means you can't verify.
Also, statements like "if {CONDITION} then begin {NO CODE} end else begin {PASCAL CODE} end;" should keep the {CONDITION} consistent from pascal to assembler no matter the optimization level, I don't know if that's done now.
   I think a modifier or a local compiler switch(that would keep the condition steady between the pascal and assembler codes) might be the best way to deal with these slowdowns, but that's something only main developers can accept. Otherwise, mass changes will lead to many slowdowns. Even now, I think there are many CPUs that don't have this huge slowdown when asked to execute the same code.
   I think this approach has a potential to be a solution not just a workaround like the pair of "nop"s. Current implementation inserts the pair of "nop"s also in functions/procedures that don't contain conditional jumps. Because it's not yet known what and how that pair influences, this might lead to slowdowns without any possible benefit whatsoever.

   When I get tired I also get curious.
I wondered what would happen if instead of modifying the "if...then...else" code produced, the loops would be modified so that the conditional jump would fail and the next line would be a "jmp loopbeginlabel".
It would be an all FFFFF...pattern no matter how many "if...then...else" statements you have there. :)
You'll have to read the next note to see the results because this one will get to bulky.


@Jeppe Johansen
"Have you tried running it through AMD VTune instead?"
   No, I didn't. At the moment, I can't say I'm much interested in how many times(percentage) a particular CPU misses something. All CPUs miss something(caches, branches...).
The code producing these anomalies is so simple, with huge slowdowns, similar codes are so often used that if the root cause would be the branch miss-prediction I'd like to "annihilate" that :).
I don't want such (branch guessing algorithm) vs. (inappropriate code to that algorithm) combinations too often :).
If two "nop"s would mess with whatever causes this I'll gladly use them.
The "nop"s are almost for free, the algorithm has been payed once the CPU has been sold. :)
Also, I'm sure this kind of situations have been discussed over and over again by many people, with different CPUs.
I have doubts that I'm able to bring something new, useful for the community, by using vTune.
   Maybe there was, but I haven't seen nowhere a similar workaround(pair of "nop"s).
Also, the influence of function/procedure calls is again something that wasn't discussed much, I think.
If these calls wouldn't have existed, most probably I wouldn't have realized the huge slowdowns...they appear to be connected on some CPUs.
And also, the TrueFalseTrueFalse... simple pattern is not an optimum pattern and I don't have a reason to believe that some CPUs are not produced, even today, without slowdowns when facing this pattern regarding branch prediction.
   A loop, a "call" and an "if...then...else" statement is a combination with huge potential to end up with significant slowdowns on some CPUs.
   Probably C has a solution for these situations but I don't know of any in Fpc. Combining loops with an "if...then...else" statement will lead to either TFTF... pattern, either TTTT.... situation where the programmer has to place the most executed part in "else".
Maybe in some situations, sticking as much as possible with an all true or with an all false pattern is a better approach than removing a simple "jmp" instruction.
Maybe by removing that instruction we do more harm than good on some CPUs. Maybe we should stick with what the pascal programmer wanted, not override his decisions if he doesn't want to.

lagprogramming

2014-10-13 21:45

reporter   ~0078206

@Do-wan Kim
   Resuming...
   I wondered what would happen if instead of modifying the "if...then...else" code produced, the loops would be modified so that the conditional jump would fail and the next line would be a "jmp loopbeginlabel".
It would be an all FFFFF...pattern no matter how many "if...then...else" statements you have there. :)


   A series of tests have been done to see if a FalseFalseFalse.... branch pattern would be ok for the AMD Mobile Sempron.
   So, codes like:

C:=0;WHILE C<=1 DO
    BEGIN
    r:=0;x:=0;
    M:=GETTICKCOUNT;FOR Z:=0 TO 500000000 DO Inc(r,q_longint(x,C));M:=GETTICKCOUNT-M;
    RESULTS.Append('Inc(r,q_longint('+inttostr(x)+','+inttostr(C)+')); '+INTTOSTR(M)+'ms');
    INC(C);
    END;

have been changed to using "if" statements instead of "for" and "while":

C:=0;
L1: IF C<=1 THEN
    BEGIN
    r:=0;x:=0;
    M:=GETTICKCOUNT;
    Z:=0;
    LL1: IF Z<>500000000 THEN
        BEGIN
        Inc(r,q_longint(x,C));
        Inc(Z);
        GOTO LL1;
        end;
    M:=GETTICKCOUNT-M;
    RESULTS.Append('Inc(r,q_longint('+inttostr(x)+','+inttostr(C)+')); '+INTTOSTR(M)+'ms');
    INC(C);
    GOTO L1;
    END;

After replacing the code that uses longints a partial test followed:
Inc(r,q_longint(0,0)); 2982ms
Inc(r,q_longint(0,1)); 3289ms
Inc(r,q_longint_inline(0,0)); 1771ms
Inc(r,q_longint_inline(0,1)); 1759ms
Inc(r,q_longint_je(0,0)); 2985ms
Inc(r,q_longint_je(0,1)); 2714ms
Inc(r,q_var_longint(0,0)); 6931ms*****
Inc(r,q_var_longint(0,1)); 3000ms*****
Inc(r,q_var_longint_inline(0,0)); 1476ms
Inc(r,q_var_longint_inline(0,1)); 1773ms
Inc(r,q_var_longint_je(0,0)); 3294ms***
Inc(r,q_var_longint_je(0,1)); 7130ms***
Inc(r,q_constref_longint(0,0)); 7165ms*****
Inc(r,q_constref_longint(0,1)); 3244ms*****
Inc(r,q_constref_longint_inline(0,0)); 1524ms
Inc(r,q_constref_longint_inline(0,1)); 1763ms
Inc(r,q_constref_longint_je(0,0)); 6819ms*****
Inc(r,q_constref_longint_je(0,1)); 2994ms*****
Inc(r,q_const_longint(0,0)); 2358ms
Inc(r,q_const_longint(0,1)); 2712ms
Inc(r,q_const_longint_inline(0,0)); 1767ms
Inc(r,q_const_longint_inline(0,1)); 1519ms
Inc(r,q_const_longint_je(0,0)); 3239ms
Inc(r,q_const_longint_je(0,1)); 3004ms

   The above "disaster" stopped me from modifying the int64 code, too. For sure the FFFFF...pattern is no better than the TFTFTF.... I don't get it, sometimes I feel like the CPU doesn't care at all about previous "experiences".
   If there would be a good pattern it's not enough to be a simple one, it has to be the TTTT...one. The above test shows that recursive "if" statements, even when arranging the code so that the "then" part is executed almost all the time, it has 50% chances to result in a big gap between code execution timings. 75% when it happens, it's against the user. When it's not against the user, the gain is too small, if there is a gain. With the huge code execution speed there's no wonder I consider building a monument to the pair of "nop"s. :)
   So, arranging the code so that the "then" part is executed most of the times(compared to "else") appears to be a sure way(the safest way) to make the code run slower on this processor.
   Regarding the TTTTT...pattern, as previously observed using "AMDSempronMobile3500pluswine" and "AMDSempronMobile3500plusx8664.txt" attachments, all anomalies appeared at the "then" part, not "else". The "if" statement was within two loops. So TTT...pattern("else" part) didn't produced anomalies, all of them appeared at "then".
   I need a little bit of time to double-check these informations but everything points to this direction. What do you think?

Do-wan Kim

2014-10-14 02:04

reporter   ~0078212

Outside if-else statements was not considered if that is not in near branch. I guess it's problem in "q_*" function, "exit" also considered True. I'm hard to say what is happen in this xD

lagprogramming

2014-10-16 12:58

reporter  

Detailed_analysis.html (170,931 bytes)   
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2//EN">

<HTML>
<HEAD>
	
	<META HTTP-EQUIV="CONTENT-TYPE" CONTENT="text/html; charset=iso-8859-1">
	<TITLE></TITLE>
	<META NAME="GENERATOR" CONTENT="LibreOffice 99999999">
	<META NAME="CREATED" CONTENT="99999999;99999999">
	<META NAME="CHANGED" CONTENT="99999999;99999999">
	
	<STYLE>
		<!-- 
		BODY,DIV,TABLE,THEAD,TBODY,TFOOT,TR,TH,TD,P { font-family:"Arial"; font-size:x-small }
		 -->
	</STYLE>
	
</HEAD>

<BODY TEXT="#000000">
<HR>
	<P><CENTER>
		<H1>Overview</H1>
		<A HREF="#table0">Foreword</A><BR>
		<A HREF="#table1">Step I</A><BR>
		<A HREF="#table2">Step II</A><BR>
		<A HREF="#table3">Step III</A><BR>
		<A HREF="#table4">Observations</A><BR>
		
	</CENTER></P>
<HR>
<A NAME="table0"><H1>Sheet 1: <EM>Foreword</EM></H1></A>
<TABLE CELLSPACING="0" COLS="1" BORDER="0">
	<COLGROUP WIDTH="1072"></COLGROUP>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">* marks an anomalies appeared after &ldquo;nop&rdquo; insertions</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">** marks anomalies removed by &ldquo;nop&rdquo; insertions</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">Conditions found within names are the conditions used in Pascal. Binary built code usually contains the opposite of the Pascal used condition. Example: &ldquo;equal&rdquo; becomes &ldquo;jne&rdquo;.</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">Inlined functions are not inserted with &ldquo;nop&rdquo;s, meaning that the same binary code is executed.</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">&ldquo;Constref&rdquo; and &ldquo;var&rdquo; usually produce the same binary code.</TD>
	</TR>
</TABLE>
<!-- ************************************************************************** -->
<HR>
<A NAME="table1"><H1>Sheet 2: <EM>Step I</EM></H1></A>
<TABLE CELLSPACING="0" COLS="4" BORDER="0">
	<COLGROUP WIDTH="296"></COLGROUP>
	<COLGROUP WIDTH="86"></COLGROUP>
	<COLGROUP WIDTH="116"></COLGROUP>
	<COLGROUP WIDTH="85"></COLGROUP>
	<TR>
		<TD HEIGHT="16" ALIGN="LEFT">Initial timings.</TD>
		<TD ALIGN="CENTER"><BR></TD>
		<TD ALIGN="CENTER"><BR></TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="16" ALIGN="LEFT"><BR></TD>
		<TD ALIGN="CENTER"><BR></TD>
		<TD ALIGN="CENTER"><BR></TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT"><BR></TD>
		<TD ALIGN="CENTER">Original[ms]</TD>
		<TD ALIGN="CENTER">NOPInserted[ms]</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__equal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2567" SDNUM="1033;">2567</TD>
		<TD ALIGN="CENTER" SDVAL="2573" SDNUM="1033;">2573</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__equal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2794" SDNUM="1033;">2794</TD>
		<TD ALIGN="CENTER" SDVAL="2808" SDNUM="1033;">2808</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__notequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2699" SDNUM="1033;">2699</TD>
		<TD ALIGN="CENTER" SDVAL="3141" SDNUM="1033;">3141</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__notequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2481" SDNUM="1033;">2481</TD>
		<TD ALIGN="CENTER" SDVAL="3061" SDNUM="1033;">3061</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__less_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2820" SDNUM="1033;">2820</TD>
		<TD ALIGN="CENTER" SDVAL="2827" SDNUM="1033;">2827</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__less_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2549" SDNUM="1033;">2549</TD>
		<TD ALIGN="CENTER" SDVAL="2558" SDNUM="1033;">2558</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__lessorequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2309" SDNUM="1033;">2309</TD>
		<TD ALIGN="CENTER" SDVAL="2320" SDNUM="1033;">2320</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__lessorequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2293" SDNUM="1033;">2293</TD>
		<TD ALIGN="CENTER" SDVAL="2293" SDNUM="1033;">2293</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__more_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2819" SDNUM="1033;">2819</TD>
		<TD ALIGN="CENTER" SDVAL="2830" SDNUM="1033;">2830</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__more_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2796" SDNUM="1033;">2796</TD>
		<TD ALIGN="CENTER" SDVAL="2807" SDNUM="1033;">2807</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__moreorequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2313" SDNUM="1033;">2313</TD>
		<TD ALIGN="CENTER" SDVAL="2316" SDNUM="1033;">2316</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__moreorequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2540" SDNUM="1033;">2540</TD>
		<TD ALIGN="CENTER" SDVAL="2547" SDNUM="1033;">2547</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__iszero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2573" SDNUM="1033;">2573</TD>
		<TD ALIGN="CENTER" SDVAL="2571" SDNUM="1033;">2571</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__iszero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2825" SDNUM="1033;">2825</TD>
		<TD ALIGN="CENTER" SDVAL="2805" SDNUM="1033;">2805</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__isnotzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2540" SDNUM="1033;">2540</TD>
		<TD ALIGN="CENTER" SDVAL="2570" SDNUM="1033;">2570</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__isnotzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2303" SDNUM="1033;">2303</TD>
		<TD ALIGN="CENTER" SDVAL="2298" SDNUM="1033;">2298</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__lessthanzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2812" SDNUM="1033;">2812</TD>
		<TD ALIGN="CENTER" SDVAL="2828" SDNUM="1033;">2828</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__lessthanzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2570" SDNUM="1033;">2570</TD>
		<TD ALIGN="CENTER" SDVAL="2576" SDNUM="1033;">2576</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__lessorequaltozero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2291" SDNUM="1033;">2291</TD>
		<TD ALIGN="CENTER" SDVAL="5758" SDNUM="1033;">5758</TD>
		<TD ALIGN="LEFT">*</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__lessorequaltozero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2287" SDNUM="1033;">2287</TD>
		<TD ALIGN="CENTER" SDVAL="5762" SDNUM="1033;">5762</TD>
		<TD ALIGN="LEFT">*</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__morethanzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2828" SDNUM="1033;">2828</TD>
		<TD ALIGN="CENTER" SDVAL="2790" SDNUM="1033;">2790</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__morethanzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2822" SDNUM="1033;">2822</TD>
		<TD ALIGN="CENTER" SDVAL="2822" SDNUM="1033;">2822</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__moreorequaltozero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2285" SDNUM="1033;">2285</TD>
		<TD ALIGN="CENTER" SDVAL="2284" SDNUM="1033;">2284</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__moreorequaltozero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2574" SDNUM="1033;">2574</TD>
		<TD ALIGN="CENTER" SDVAL="2563" SDNUM="1033;">2563</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_equal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6123" SDNUM="1033;">6123</TD>
		<TD ALIGN="CENTER" SDVAL="2542" SDNUM="1033;">2542</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_equal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2795" SDNUM="1033;">2795</TD>
		<TD ALIGN="CENTER" SDVAL="2821" SDNUM="1033;">2821</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_notequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2821" SDNUM="1033;">2821</TD>
		<TD ALIGN="CENTER" SDVAL="2816" SDNUM="1033;">2816</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_notequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6127" SDNUM="1033;">6127</TD>
		<TD ALIGN="CENTER" SDVAL="2597" SDNUM="1033;">2597</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_less_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2820" SDNUM="1033;">2820</TD>
		<TD ALIGN="CENTER" SDVAL="2822" SDNUM="1033;">2822</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_less_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6159" SDNUM="1033;">6159</TD>
		<TD ALIGN="CENTER" SDVAL="2613" SDNUM="1033;">2613</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_lessorequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6126" SDNUM="1033;">6126</TD>
		<TD ALIGN="CENTER" SDVAL="2568" SDNUM="1033;">2568</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_lessorequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6127" SDNUM="1033;">6127</TD>
		<TD ALIGN="CENTER" SDVAL="2544" SDNUM="1033;">2544</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_more_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2825" SDNUM="1033;">2825</TD>
		<TD ALIGN="CENTER" SDVAL="2818" SDNUM="1033;">2818</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_more_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2819" SDNUM="1033;">2819</TD>
		<TD ALIGN="CENTER" SDVAL="2790" SDNUM="1033;">2790</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_moreorequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6121" SDNUM="1033;">6121</TD>
		<TD ALIGN="CENTER" SDVAL="2568" SDNUM="1033;">2568</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_moreorequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2792" SDNUM="1033;">2792</TD>
		<TD ALIGN="CENTER" SDVAL="2792" SDNUM="1033;">2792</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_iszero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6154" SDNUM="1033;">6154</TD>
		<TD ALIGN="CENTER" SDVAL="2566" SDNUM="1033;">2566</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_iszero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2793" SDNUM="1033;">2793</TD>
		<TD ALIGN="CENTER" SDVAL="2796" SDNUM="1033;">2796</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_isnotzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2820" SDNUM="1033;">2820</TD>
		<TD ALIGN="CENTER" SDVAL="2815" SDNUM="1033;">2815</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_isnotzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6144" SDNUM="1033;">6144</TD>
		<TD ALIGN="CENTER" SDVAL="2573" SDNUM="1033;">2573</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_lessthanzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2800" SDNUM="1033;">2800</TD>
		<TD ALIGN="CENTER" SDVAL="2793" SDNUM="1033;">2793</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_lessthanzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6175" SDNUM="1033;">6175</TD>
		<TD ALIGN="CENTER" SDVAL="2568" SDNUM="1033;">2568</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_lessorequaltozero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6182" SDNUM="1033;">6182</TD>
		<TD ALIGN="CENTER" SDVAL="2601" SDNUM="1033;">2601</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_lessorequaltozero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6186" SDNUM="1033;">6186</TD>
		<TD ALIGN="CENTER" SDVAL="2632" SDNUM="1033;">2632</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_morethanzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2879" SDNUM="1033;">2879</TD>
		<TD ALIGN="CENTER" SDVAL="2853" SDNUM="1033;">2853</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_morethanzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2846" SDNUM="1033;">2846</TD>
		<TD ALIGN="CENTER" SDVAL="2883" SDNUM="1033;">2883</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_moreorequaltozero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6201" SDNUM="1033;">6201</TD>
		<TD ALIGN="CENTER" SDVAL="2601" SDNUM="1033;">2601</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_moreorequaltozero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2846" SDNUM="1033;">2846</TD>
		<TD ALIGN="CENTER" SDVAL="2882" SDNUM="1033;">2882</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_equal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2628" SDNUM="1033;">2628</TD>
		<TD ALIGN="CENTER" SDVAL="2608" SDNUM="1033;">2608</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_equal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2846" SDNUM="1033;">2846</TD>
		<TD ALIGN="CENTER" SDVAL="2880" SDNUM="1033;">2880</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_notequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2625" SDNUM="1033;">2625</TD>
		<TD ALIGN="CENTER" SDVAL="2627" SDNUM="1033;">2627</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_notequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2345" SDNUM="1033;">2345</TD>
		<TD ALIGN="CENTER" SDVAL="2358" SDNUM="1033;">2358</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_less_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2875" SDNUM="1033;">2875</TD>
		<TD ALIGN="CENTER" SDVAL="2881" SDNUM="1033;">2881</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_less_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2601" SDNUM="1033;">2601</TD>
		<TD ALIGN="CENTER" SDVAL="2604" SDNUM="1033;">2604</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_lessorequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2373" SDNUM="1033;">2373</TD>
		<TD ALIGN="CENTER" SDVAL="2387" SDNUM="1033;">2387</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_lessorequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2346" SDNUM="1033;">2346</TD>
		<TD ALIGN="CENTER" SDVAL="2348" SDNUM="1033;">2348</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_more_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2871" SDNUM="1033;">2871</TD>
		<TD ALIGN="CENTER" SDVAL="2881" SDNUM="1033;">2881</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_more_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2856" SDNUM="1033;">2856</TD>
		<TD ALIGN="CENTER" SDVAL="2860" SDNUM="1033;">2860</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_moreorequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="3009" SDNUM="1033;">3009</TD>
		<TD ALIGN="CENTER" SDVAL="2998" SDNUM="1033;">2998</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_moreorequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="3027" SDNUM="1033;">3027</TD>
		<TD ALIGN="CENTER" SDVAL="3270" SDNUM="1033;">3270</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_iszero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2597" SDNUM="1033;">2597</TD>
		<TD ALIGN="CENTER" SDVAL="2630" SDNUM="1033;">2630</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_iszero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2875" SDNUM="1033;">2875</TD>
		<TD ALIGN="CENTER" SDVAL="2883" SDNUM="1033;">2883</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_isnotzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2602" SDNUM="1033;">2602</TD>
		<TD ALIGN="CENTER" SDVAL="2602" SDNUM="1033;">2602</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_isnotzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2372" SDNUM="1033;">2372</TD>
		<TD ALIGN="CENTER" SDVAL="2377" SDNUM="1033;">2377</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_lessthanzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2853" SDNUM="1033;">2853</TD>
		<TD ALIGN="CENTER" SDVAL="2857" SDNUM="1033;">2857</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_lessthanzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2629" SDNUM="1033;">2629</TD>
		<TD ALIGN="CENTER" SDVAL="2634" SDNUM="1033;">2634</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_lessorequaltozero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2345" SDNUM="1033;">2345</TD>
		<TD ALIGN="CENTER" SDVAL="2351" SDNUM="1033;">2351</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_lessorequaltozero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2367" SDNUM="1033;">2367</TD>
		<TD ALIGN="CENTER" SDVAL="2377" SDNUM="1033;">2377</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_morethanzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2851" SDNUM="1033;">2851</TD>
		<TD ALIGN="CENTER" SDVAL="2860" SDNUM="1033;">2860</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_morethanzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2886" SDNUM="1033;">2886</TD>
		<TD ALIGN="CENTER" SDVAL="2883" SDNUM="1033;">2883</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_moreorequaltozero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2343" SDNUM="1033;">2343</TD>
		<TD ALIGN="CENTER" SDVAL="2356" SDNUM="1033;">2356</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_moreorequaltozero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2625" SDNUM="1033;">2625</TD>
		<TD ALIGN="CENTER" SDVAL="2629" SDNUM="1033;">2629</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_equal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6170" SDNUM="1033;">6170</TD>
		<TD ALIGN="CENTER" SDVAL="2608" SDNUM="1033;">2608</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_equal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2881" SDNUM="1033;">2881</TD>
		<TD ALIGN="CENTER" SDVAL="2882" SDNUM="1033;">2882</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_notequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2849" SDNUM="1033;">2849</TD>
		<TD ALIGN="CENTER" SDVAL="2862" SDNUM="1033;">2862</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_notequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6171" SDNUM="1033;">6171</TD>
		<TD ALIGN="CENTER" SDVAL="2629" SDNUM="1033;">2629</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_less_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2878" SDNUM="1033;">2878</TD>
		<TD ALIGN="CENTER" SDVAL="2884" SDNUM="1033;">2884</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_less_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6171" SDNUM="1033;">6171</TD>
		<TD ALIGN="CENTER" SDVAL="2611" SDNUM="1033;">2611</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_lessorequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6193" SDNUM="1033;">6193</TD>
		<TD ALIGN="CENTER" SDVAL="2634" SDNUM="1033;">2634</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_lessorequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6172" SDNUM="1033;">6172</TD>
		<TD ALIGN="CENTER" SDVAL="2604" SDNUM="1033;">2604</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_more_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2857" SDNUM="1033;">2857</TD>
		<TD ALIGN="CENTER" SDVAL="2890" SDNUM="1033;">2890</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_more_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2876" SDNUM="1033;">2876</TD>
		<TD ALIGN="CENTER" SDVAL="2859" SDNUM="1033;">2859</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_moreorequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6169" SDNUM="1033;">6169</TD>
		<TD ALIGN="CENTER" SDVAL="2633" SDNUM="1033;">2633</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_moreorequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2876" SDNUM="1033;">2876</TD>
		<TD ALIGN="CENTER" SDVAL="2858" SDNUM="1033;">2858</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_iszero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6179" SDNUM="1033;">6179</TD>
		<TD ALIGN="CENTER" SDVAL="2630" SDNUM="1033;">2630</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_iszero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2877" SDNUM="1033;">2877</TD>
		<TD ALIGN="CENTER" SDVAL="2864" SDNUM="1033;">2864</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_isnotzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2850" SDNUM="1033;">2850</TD>
		<TD ALIGN="CENTER" SDVAL="2883" SDNUM="1033;">2883</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_isnotzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6186" SDNUM="1033;">6186</TD>
		<TD ALIGN="CENTER" SDVAL="2631" SDNUM="1033;">2631</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_lessthanzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2875" SDNUM="1033;">2875</TD>
		<TD ALIGN="CENTER" SDVAL="2862" SDNUM="1033;">2862</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_lessthanzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6169" SDNUM="1033;">6169</TD>
		<TD ALIGN="CENTER" SDVAL="2632" SDNUM="1033;">2632</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_lessorequaltozero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6170" SDNUM="1033;">6170</TD>
		<TD ALIGN="CENTER" SDVAL="2609" SDNUM="1033;">2609</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_lessorequaltozero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6193" SDNUM="1033;">6193</TD>
		<TD ALIGN="CENTER" SDVAL="2629" SDNUM="1033;">2629</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_morethanzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2857" SDNUM="1033;">2857</TD>
		<TD ALIGN="CENTER" SDVAL="2862" SDNUM="1033;">2862</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_morethanzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2874" SDNUM="1033;">2874</TD>
		<TD ALIGN="CENTER" SDVAL="2889" SDNUM="1033;">2889</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_moreorequaltozero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6175" SDNUM="1033;">6175</TD>
		<TD ALIGN="CENTER" SDVAL="2604" SDNUM="1033;">2604</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_moreorequaltozero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2898" SDNUM="1033;">2898</TD>
		<TD ALIGN="CENTER" SDVAL="2903" SDNUM="1033;">2903</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__equal_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1842" SDNUM="1033;">1842</TD>
		<TD ALIGN="CENTER" SDVAL="1848" SDNUM="1033;">1848</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__equal_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1588" SDNUM="1033;">1588</TD>
		<TD ALIGN="CENTER" SDVAL="1626" SDNUM="1033;">1626</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__notequal_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1621" SDNUM="1033;">1621</TD>
		<TD ALIGN="CENTER" SDVAL="1602" SDNUM="1033;">1602</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__notequal_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1839" SDNUM="1033;">1839</TD>
		<TD ALIGN="CENTER" SDVAL="1849" SDNUM="1033;">1849</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__less_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1594" SDNUM="1033;">1594</TD>
		<TD ALIGN="CENTER" SDVAL="1626" SDNUM="1033;">1626</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__less_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1870" SDNUM="1033;">1870</TD>
		<TD ALIGN="CENTER" SDVAL="1850" SDNUM="1033;">1850</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__lessorequal_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1842" SDNUM="1033;">1842</TD>
		<TD ALIGN="CENTER" SDVAL="1847" SDNUM="1033;">1847</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__lessorequal_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1850" SDNUM="1033;">1850</TD>
		<TD ALIGN="CENTER" SDVAL="1873" SDNUM="1033;">1873</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__more_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1612" SDNUM="1033;">1612</TD>
		<TD ALIGN="CENTER" SDVAL="1601" SDNUM="1033;">1601</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__more_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1592" SDNUM="1033;">1592</TD>
		<TD ALIGN="CENTER" SDVAL="1603" SDNUM="1033;">1603</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__moreorequal_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1842" SDNUM="1033;">1842</TD>
		<TD ALIGN="CENTER" SDVAL="1875" SDNUM="1033;">1875</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__moreorequal_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1621" SDNUM="1033;">1621</TD>
		<TD ALIGN="CENTER" SDVAL="1603" SDNUM="1033;">1603</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__iszero_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1843" SDNUM="1033;">1843</TD>
		<TD ALIGN="CENTER" SDVAL="1850" SDNUM="1033;">1850</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__iszero_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1596" SDNUM="1033;">1596</TD>
		<TD ALIGN="CENTER" SDVAL="1626" SDNUM="1033;">1626</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__isnotzero_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1619" SDNUM="1033;">1619</TD>
		<TD ALIGN="CENTER" SDVAL="1596" SDNUM="1033;">1596</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__isnotzero_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1838" SDNUM="1033;">1838</TD>
		<TD ALIGN="CENTER" SDVAL="1848" SDNUM="1033;">1848</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__lessthanzero_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1593" SDNUM="1033;">1593</TD>
		<TD ALIGN="CENTER" SDVAL="1625" SDNUM="1033;">1625</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__lessthanzero_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1868" SDNUM="1033;">1868</TD>
		<TD ALIGN="CENTER" SDVAL="1850" SDNUM="1033;">1850</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__lessorequaltozero_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1839" SDNUM="1033;">1839</TD>
		<TD ALIGN="CENTER" SDVAL="1874" SDNUM="1033;">1874</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__lessorequaltozero_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1867" SDNUM="1033;">1867</TD>
		<TD ALIGN="CENTER" SDVAL="1848" SDNUM="1033;">1848</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__morethanzero_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1594" SDNUM="1033;">1594</TD>
		<TD ALIGN="CENTER" SDVAL="1613" SDNUM="1033;">1613</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__morethanzero_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1593" SDNUM="1033;">1593</TD>
		<TD ALIGN="CENTER" SDVAL="1623" SDNUM="1033;">1623</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__moreorequaltozero_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1866" SDNUM="1033;">1866</TD>
		<TD ALIGN="CENTER" SDVAL="1844" SDNUM="1033;">1844</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__moreorequaltozero_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1587" SDNUM="1033;">1587</TD>
		<TD ALIGN="CENTER" SDVAL="1599" SDNUM="1033;">1599</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_equal_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1843" SDNUM="1033;">1843</TD>
		<TD ALIGN="CENTER" SDVAL="1875" SDNUM="1033;">1875</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_equal_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1617" SDNUM="1033;">1617</TD>
		<TD ALIGN="CENTER" SDVAL="1604" SDNUM="1033;">1604</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_notequal_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1592" SDNUM="1033;">1592</TD>
		<TD ALIGN="CENTER" SDVAL="1602" SDNUM="1033;">1602</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_notequal_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1842" SDNUM="1033;">1842</TD>
		<TD ALIGN="CENTER" SDVAL="1868" SDNUM="1033;">1868</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_less_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1618" SDNUM="1033;">1618</TD>
		<TD ALIGN="CENTER" SDVAL="1596" SDNUM="1033;">1596</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_less_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1846" SDNUM="1033;">1846</TD>
		<TD ALIGN="CENTER" SDVAL="1840" SDNUM="1033;">1840</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_lessorequal_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1838" SDNUM="1033;">1838</TD>
		<TD ALIGN="CENTER" SDVAL="1864" SDNUM="1033;">1864</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_lessorequal_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1862" SDNUM="1033;">1862</TD>
		<TD ALIGN="CENTER" SDVAL="1843" SDNUM="1033;">1843</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_more_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1593" SDNUM="1033;">1593</TD>
		<TD ALIGN="CENTER" SDVAL="1596" SDNUM="1033;">1596</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_more_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1596" SDNUM="1033;">1596</TD>
		<TD ALIGN="CENTER" SDVAL="1619" SDNUM="1033;">1619</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_moreorequal_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1864" SDNUM="1033;">1864</TD>
		<TD ALIGN="CENTER" SDVAL="1843" SDNUM="1033;">1843</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_moreorequal_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1594" SDNUM="1033;">1594</TD>
		<TD ALIGN="CENTER" SDVAL="1597" SDNUM="1033;">1597</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_iszero_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1840" SDNUM="1033;">1840</TD>
		<TD ALIGN="CENTER" SDVAL="1868" SDNUM="1033;">1868</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_iszero_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1614" SDNUM="1033;">1614</TD>
		<TD ALIGN="CENTER" SDVAL="1589" SDNUM="1033;">1589</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_isnotzero_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1595" SDNUM="1033;">1595</TD>
		<TD ALIGN="CENTER" SDVAL="1595" SDNUM="1033;">1595</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_isnotzero_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1840" SDNUM="1033;">1840</TD>
		<TD ALIGN="CENTER" SDVAL="1867" SDNUM="1033;">1867</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_lessthanzero_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1620" SDNUM="1033;">1620</TD>
		<TD ALIGN="CENTER" SDVAL="1595" SDNUM="1033;">1595</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_lessthanzero_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1839" SDNUM="1033;">1839</TD>
		<TD ALIGN="CENTER" SDVAL="1845" SDNUM="1033;">1845</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_lessorequaltozero_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1843" SDNUM="1033;">1843</TD>
		<TD ALIGN="CENTER" SDVAL="1867" SDNUM="1033;">1867</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_lessorequaltozero_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1867" SDNUM="1033;">1867</TD>
		<TD ALIGN="CENTER" SDVAL="1840" SDNUM="1033;">1840</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_morethanzero_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1600" SDNUM="1033;">1600</TD>
		<TD ALIGN="CENTER" SDVAL="1617" SDNUM="1033;">1617</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_morethanzero_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1588" SDNUM="1033;">1588</TD>
		<TD ALIGN="CENTER" SDVAL="1592" SDNUM="1033;">1592</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_moreorequaltozero_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1869" SDNUM="1033;">1869</TD>
		<TD ALIGN="CENTER" SDVAL="1850" SDNUM="1033;">1850</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_moreorequaltozero_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1592" SDNUM="1033;">1592</TD>
		<TD ALIGN="CENTER" SDVAL="1620" SDNUM="1033;">1620</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_equal_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1866" SDNUM="1033;">1866</TD>
		<TD ALIGN="CENTER" SDVAL="1840" SDNUM="1033;">1840</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_equal_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1594" SDNUM="1033;">1594</TD>
		<TD ALIGN="CENTER" SDVAL="1598" SDNUM="1033;">1598</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_notequal_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1592" SDNUM="1033;">1592</TD>
		<TD ALIGN="CENTER" SDVAL="1621" SDNUM="1033;">1621</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_notequal_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1868" SDNUM="1033;">1868</TD>
		<TD ALIGN="CENTER" SDVAL="1840" SDNUM="1033;">1840</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_less_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1587" SDNUM="1033;">1587</TD>
		<TD ALIGN="CENTER" SDVAL="1594" SDNUM="1033;">1594</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_less_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1843" SDNUM="1033;">1843</TD>
		<TD ALIGN="CENTER" SDVAL="1866" SDNUM="1033;">1866</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_lessorequal_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1864" SDNUM="1033;">1864</TD>
		<TD ALIGN="CENTER" SDVAL="1844" SDNUM="1033;">1844</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_lessorequal_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1843" SDNUM="1033;">1843</TD>
		<TD ALIGN="CENTER" SDVAL="1846" SDNUM="1033;">1846</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_more_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1595" SDNUM="1033;">1595</TD>
		<TD ALIGN="CENTER" SDVAL="1617" SDNUM="1033;">1617</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_more_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1619" SDNUM="1033;">1619</TD>
		<TD ALIGN="CENTER" SDVAL="1593" SDNUM="1033;">1593</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_moreorequal_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1842" SDNUM="1033;">1842</TD>
		<TD ALIGN="CENTER" SDVAL="1845" SDNUM="1033;">1845</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_moreorequal_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1589" SDNUM="1033;">1589</TD>
		<TD ALIGN="CENTER" SDVAL="1614" SDNUM="1033;">1614</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_iszero_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1867" SDNUM="1033;">1867</TD>
		<TD ALIGN="CENTER" SDVAL="1844" SDNUM="1033;">1844</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_iszero_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1591" SDNUM="1033;">1591</TD>
		<TD ALIGN="CENTER" SDVAL="1594" SDNUM="1033;">1594</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_isnotzero_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1595" SDNUM="1033;">1595</TD>
		<TD ALIGN="CENTER" SDVAL="1618" SDNUM="1033;">1618</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_isnotzero_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1869" SDNUM="1033;">1869</TD>
		<TD ALIGN="CENTER" SDVAL="1846" SDNUM="1033;">1846</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_lessthanzero_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1595" SDNUM="1033;">1595</TD>
		<TD ALIGN="CENTER" SDVAL="1598" SDNUM="1033;">1598</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_lessthanzero_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1843" SDNUM="1033;">1843</TD>
		<TD ALIGN="CENTER" SDVAL="1868" SDNUM="1033;">1868</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_lessorequaltozero_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1868" SDNUM="1033;">1868</TD>
		<TD ALIGN="CENTER" SDVAL="1841" SDNUM="1033;">1841</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_lessorequaltozero_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1836" SDNUM="1033;">1836</TD>
		<TD ALIGN="CENTER" SDVAL="1865" SDNUM="1033;">1865</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_morethanzero_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1595" SDNUM="1033;">1595</TD>
		<TD ALIGN="CENTER" SDVAL="1595" SDNUM="1033;">1595</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_morethanzero_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1621" SDNUM="1033;">1621</TD>
		<TD ALIGN="CENTER" SDVAL="1600" SDNUM="1033;">1600</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_moreorequaltozero_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1840" SDNUM="1033;">1840</TD>
		<TD ALIGN="CENTER" SDVAL="1865" SDNUM="1033;">1865</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_moreorequaltozero_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1599" SDNUM="1033;">1599</TD>
		<TD ALIGN="CENTER" SDVAL="1600" SDNUM="1033;">1600</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_equal_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2370" SDNUM="1033;">2370</TD>
		<TD ALIGN="CENTER" SDVAL="2347" SDNUM="1033;">2347</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_equal_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2097" SDNUM="1033;">2097</TD>
		<TD ALIGN="CENTER" SDVAL="2120" SDNUM="1033;">2120</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_notequal_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2120" SDNUM="1033;">2120</TD>
		<TD ALIGN="CENTER" SDVAL="2099" SDNUM="1033;">2099</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_notequal_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2097" SDNUM="1033;">2097</TD>
		<TD ALIGN="CENTER" SDVAL="2122" SDNUM="1033;">2122</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_less_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2119" SDNUM="1033;">2119</TD>
		<TD ALIGN="CENTER" SDVAL="2094" SDNUM="1033;">2094</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_less_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2348" SDNUM="1033;">2348</TD>
		<TD ALIGN="CENTER" SDVAL="2350" SDNUM="1033;">2350</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_lessorequal_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2120" SDNUM="1033;">2120</TD>
		<TD ALIGN="CENTER" SDVAL="2121" SDNUM="1033;">2121</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_lessorequal_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2102" SDNUM="1033;">2102</TD>
		<TD ALIGN="CENTER" SDVAL="2096" SDNUM="1033;">2096</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_more_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2097" SDNUM="1033;">2097</TD>
		<TD ALIGN="CENTER" SDVAL="2126" SDNUM="1033;">2126</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_more_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2124" SDNUM="1033;">2124</TD>
		<TD ALIGN="CENTER" SDVAL="2102" SDNUM="1033;">2102</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_moreorequal_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2095" SDNUM="1033;">2095</TD>
		<TD ALIGN="CENTER" SDVAL="2120" SDNUM="1033;">2120</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_moreorequal_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2120" SDNUM="1033;">2120</TD>
		<TD ALIGN="CENTER" SDVAL="2095" SDNUM="1033;">2095</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_iszero_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2349" SDNUM="1033;">2349</TD>
		<TD ALIGN="CENTER" SDVAL="2350" SDNUM="1033;">2350</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_iszero_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2118" SDNUM="1033;">2118</TD>
		<TD ALIGN="CENTER" SDVAL="2119" SDNUM="1033;">2119</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_isnotzero_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2095" SDNUM="1033;">2095</TD>
		<TD ALIGN="CENTER" SDVAL="2097" SDNUM="1033;">2097</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_isnotzero_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2100" SDNUM="1033;">2100</TD>
		<TD ALIGN="CENTER" SDVAL="2122" SDNUM="1033;">2122</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_lessthanzero_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2121" SDNUM="1033;">2121</TD>
		<TD ALIGN="CENTER" SDVAL="2100" SDNUM="1033;">2100</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_lessthanzero_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2345" SDNUM="1033;">2345</TD>
		<TD ALIGN="CENTER" SDVAL="2371" SDNUM="1033;">2371</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_lessorequaltozero_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2122" SDNUM="1033;">2122</TD>
		<TD ALIGN="CENTER" SDVAL="2099" SDNUM="1033;">2099</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_lessorequaltozero_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2095" SDNUM="1033;">2095</TD>
		<TD ALIGN="CENTER" SDVAL="2096" SDNUM="1033;">2096</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_morethanzero_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2121" SDNUM="1033;">2121</TD>
		<TD ALIGN="CENTER" SDVAL="2120" SDNUM="1033;">2120</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_morethanzero_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2098" SDNUM="1033;">2098</TD>
		<TD ALIGN="CENTER" SDVAL="2214" SDNUM="1033;">2214</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_moreorequaltozero_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2094" SDNUM="1033;">2094</TD>
		<TD ALIGN="CENTER" SDVAL="2128" SDNUM="1033;">2128</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_moreorequaltozero_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2129" SDNUM="1033;">2129</TD>
		<TD ALIGN="CENTER" SDVAL="2095" SDNUM="1033;">2095</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="16" ALIGN="LEFT">int64__equal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2601" SDNUM="1033;">2601</TD>
		<TD ALIGN="CENTER" SDVAL="2625" SDNUM="1033;">2625</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="16" ALIGN="LEFT">int64__equal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2375" SDNUM="1033;">2375</TD>
		<TD ALIGN="CENTER" SDVAL="2349" SDNUM="1033;">2349</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__notequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2600" SDNUM="1033;">2600</TD>
		<TD ALIGN="CENTER" SDVAL="2626" SDNUM="1033;">2626</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__notequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2885" SDNUM="1033;">2885</TD>
		<TD ALIGN="CENTER" SDVAL="2859" SDNUM="1033;">2859</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="16" ALIGN="LEFT">int64__less_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2345" SDNUM="1033;">2345</TD>
		<TD ALIGN="CENTER" SDVAL="2370" SDNUM="1033;">2370</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="16" ALIGN="LEFT">int64__less_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2628" SDNUM="1033;">2628</TD>
		<TD ALIGN="CENTER" SDVAL="2604" SDNUM="1033;">2604</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__lessorequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2856" SDNUM="1033;">2856</TD>
		<TD ALIGN="CENTER" SDVAL="2881" SDNUM="1033;">2881</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__lessorequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2878" SDNUM="1033;">2878</TD>
		<TD ALIGN="CENTER" SDVAL="2854" SDNUM="1033;">2854</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="16" ALIGN="LEFT">int64__more_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2545" SDNUM="1033;">2545</TD>
		<TD ALIGN="CENTER" SDVAL="2375" SDNUM="1033;">2375</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="16" ALIGN="LEFT">int64__more_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2418" SDNUM="1033;">2418</TD>
		<TD ALIGN="CENTER" SDVAL="2522" SDNUM="1033;">2522</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__moreorequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2897" SDNUM="1033;">2897</TD>
		<TD ALIGN="CENTER" SDVAL="2896" SDNUM="1033;">2896</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__moreorequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2606" SDNUM="1033;">2606</TD>
		<TD ALIGN="CENTER" SDVAL="2631" SDNUM="1033;">2631</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__iszero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2630" SDNUM="1033;">2630</TD>
		<TD ALIGN="CENTER" SDVAL="2603" SDNUM="1033;">2603</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__iszero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2346" SDNUM="1033;">2346</TD>
		<TD ALIGN="CENTER" SDVAL="2349" SDNUM="1033;">2349</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__isnotzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2625" SDNUM="1033;">2625</TD>
		<TD ALIGN="CENTER" SDVAL="2624" SDNUM="1033;">2624</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__isnotzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2858" SDNUM="1033;">2858</TD>
		<TD ALIGN="CENTER" SDVAL="2883" SDNUM="1033;">2883</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__lessthanzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2370" SDNUM="1033;">2370</TD>
		<TD ALIGN="CENTER" SDVAL="2347" SDNUM="1033;">2347</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__lessthanzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2598" SDNUM="1033;">2598</TD>
		<TD ALIGN="CENTER" SDVAL="2622" SDNUM="1033;">2622</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__lessorequaltozero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2879" SDNUM="1033;">2879</TD>
		<TD ALIGN="CENTER" SDVAL="2854" SDNUM="1033;">2854</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__lessorequaltozero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2851" SDNUM="1033;">2851</TD>
		<TD ALIGN="CENTER" SDVAL="2877" SDNUM="1033;">2877</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__morethanzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2371" SDNUM="1033;">2371</TD>
		<TD ALIGN="CENTER" SDVAL="2351" SDNUM="1033;">2351</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__morethanzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2349" SDNUM="1033;">2349</TD>
		<TD ALIGN="CENTER" SDVAL="2371" SDNUM="1033;">2371</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__moreorequaltozero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2878" SDNUM="1033;">2878</TD>
		<TD ALIGN="CENTER" SDVAL="2854" SDNUM="1033;">2854</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__moreorequaltozero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2600" SDNUM="1033;">2600</TD>
		<TD ALIGN="CENTER" SDVAL="2625" SDNUM="1033;">2625</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="16" ALIGN="LEFT">int64_var_equal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6192" SDNUM="1033;">6192</TD>
		<TD ALIGN="CENTER" SDVAL="3114" SDNUM="1033;">3114</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="16" ALIGN="LEFT">int64_var_equal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2528" SDNUM="1033;">2528</TD>
		<TD ALIGN="CENTER" SDVAL="2888" SDNUM="1033;">2888</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_notequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2625" SDNUM="1033;">2625</TD>
		<TD ALIGN="CENTER" SDVAL="2877" SDNUM="1033;">2877</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_notequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6422" SDNUM="1033;">6422</TD>
		<TD ALIGN="CENTER" SDVAL="3105" SDNUM="1033;">3105</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="16" ALIGN="LEFT">int64_var_less_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2346" SDNUM="1033;">2346</TD>
		<TD ALIGN="CENTER" SDVAL="2622" SDNUM="1033;">2622</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="16" ALIGN="LEFT">int64_var_less_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6192" SDNUM="1033;">6192</TD>
		<TD ALIGN="CENTER" SDVAL="2852" SDNUM="1033;">2852</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_lessorequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6429" SDNUM="1033;">6429</TD>
		<TD ALIGN="CENTER" SDVAL="3132" SDNUM="1033;">3132</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_lessorequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6424" SDNUM="1033;">6424</TD>
		<TD ALIGN="CENTER" SDVAL="3129" SDNUM="1033;">3129</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="16" ALIGN="LEFT">int64_var_more_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2366" SDNUM="1033;">2366</TD>
		<TD ALIGN="CENTER" SDVAL="2597" SDNUM="1033;">2597</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="16" ALIGN="LEFT">int64_var_more_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2345" SDNUM="1033;">2345</TD>
		<TD ALIGN="CENTER" SDVAL="2625" SDNUM="1033;">2625</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_moreorequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6421" SDNUM="1033;">6421</TD>
		<TD ALIGN="CENTER" SDVAL="3105" SDNUM="1033;">3105</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_moreorequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2627" SDNUM="1033;">2627</TD>
		<TD ALIGN="CENTER" SDVAL="2883" SDNUM="1033;">2883</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_iszero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6169" SDNUM="1033;">6169</TD>
		<TD ALIGN="CENTER" SDVAL="2850" SDNUM="1033;">2850</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_iszero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2366" SDNUM="1033;">2366</TD>
		<TD ALIGN="CENTER" SDVAL="2620" SDNUM="1033;">2620</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_isnotzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2595" SDNUM="1033;">2595</TD>
		<TD ALIGN="CENTER" SDVAL="2854" SDNUM="1033;">2854</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_isnotzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6419" SDNUM="1033;">6419</TD>
		<TD ALIGN="CENTER" SDVAL="3125" SDNUM="1033;">3125</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_lessthanzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="5827" SDNUM="1033;">5827</TD>
		<TD ALIGN="CENTER" SDVAL="4066" SDNUM="1033;">4066</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_lessthanzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6167" SDNUM="1033;">6167</TD>
		<TD ALIGN="CENTER" SDVAL="5619" SDNUM="1033;">5619</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_lessorequaltozero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6422" SDNUM="1033;">6422</TD>
		<TD ALIGN="CENTER" SDVAL="3128" SDNUM="1033;">3128</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_lessorequaltozero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6426" SDNUM="1033;">6426</TD>
		<TD ALIGN="CENTER" SDVAL="3100" SDNUM="1033;">3100</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_morethanzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2367" SDNUM="1033;">2367</TD>
		<TD ALIGN="CENTER" SDVAL="2623" SDNUM="1033;">2623</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_morethanzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2340" SDNUM="1033;">2340</TD>
		<TD ALIGN="CENTER" SDVAL="2593" SDNUM="1033;">2593</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_moreorequaltozero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6444" SDNUM="1033;">6444</TD>
		<TD ALIGN="CENTER" SDVAL="3128" SDNUM="1033;">3128</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_moreorequaltozero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2599" SDNUM="1033;">2599</TD>
		<TD ALIGN="CENTER" SDVAL="2850" SDNUM="1033;">2850</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_equal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2622" SDNUM="1033;">2622</TD>
		<TD ALIGN="CENTER" SDVAL="2622" SDNUM="1033;">2622</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_equal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2343" SDNUM="1033;">2343</TD>
		<TD ALIGN="CENTER" SDVAL="2339" SDNUM="1033;">2339</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_notequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2623" SDNUM="1033;">2623</TD>
		<TD ALIGN="CENTER" SDVAL="2629" SDNUM="1033;">2629</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_notequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2850" SDNUM="1033;">2850</TD>
		<TD ALIGN="CENTER" SDVAL="2871" SDNUM="1033;">2871</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_less_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2370" SDNUM="1033;">2370</TD>
		<TD ALIGN="CENTER" SDVAL="2343" SDNUM="1033;">2343</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_less_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2594" SDNUM="1033;">2594</TD>
		<TD ALIGN="CENTER" SDVAL="2626" SDNUM="1033;">2626</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_lessorequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2879" SDNUM="1033;">2879</TD>
		<TD ALIGN="CENTER" SDVAL="2849" SDNUM="1033;">2849</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_lessorequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2849" SDNUM="1033;">2849</TD>
		<TD ALIGN="CENTER" SDVAL="2873" SDNUM="1033;">2873</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_more_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2547" SDNUM="1033;">2547</TD>
		<TD ALIGN="CENTER" SDVAL="2520" SDNUM="1033;">2520</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_more_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2526" SDNUM="1033;">2526</TD>
		<TD ALIGN="CENTER" SDVAL="2554" SDNUM="1033;">2554</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_moreorequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2870" SDNUM="1033;">2870</TD>
		<TD ALIGN="CENTER" SDVAL="2847" SDNUM="1033;">2847</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_moreorequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2624" SDNUM="1033;">2624</TD>
		<TD ALIGN="CENTER" SDVAL="2628" SDNUM="1033;">2628</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_iszero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2600" SDNUM="1033;">2600</TD>
		<TD ALIGN="CENTER" SDVAL="2595" SDNUM="1033;">2595</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_iszero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2368" SDNUM="1033;">2368</TD>
		<TD ALIGN="CENTER" SDVAL="2370" SDNUM="1033;">2370</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_isnotzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2595" SDNUM="1033;">2595</TD>
		<TD ALIGN="CENTER" SDVAL="2599" SDNUM="1033;">2599</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_isnotzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2879" SDNUM="1033;">2879</TD>
		<TD ALIGN="CENTER" SDVAL="2878" SDNUM="1033;">2878</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_lessthanzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2340" SDNUM="1033;">2340</TD>
		<TD ALIGN="CENTER" SDVAL="2342" SDNUM="1033;">2342</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_lessthanzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2619" SDNUM="1033;">2619</TD>
		<TD ALIGN="CENTER" SDVAL="2620" SDNUM="1033;">2620</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_lessorequaltozero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2860" SDNUM="1033;">2860</TD>
		<TD ALIGN="CENTER" SDVAL="2852" SDNUM="1033;">2852</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_lessorequaltozero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2874" SDNUM="1033;">2874</TD>
		<TD ALIGN="CENTER" SDVAL="2875" SDNUM="1033;">2875</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_morethanzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2345" SDNUM="1033;">2345</TD>
		<TD ALIGN="CENTER" SDVAL="2370" SDNUM="1033;">2370</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_morethanzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2366" SDNUM="1033;">2366</TD>
		<TD ALIGN="CENTER" SDVAL="2346" SDNUM="1033;">2346</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_moreorequaltozero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2853" SDNUM="1033;">2853</TD>
		<TD ALIGN="CENTER" SDVAL="2875" SDNUM="1033;">2875</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_moreorequaltozero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2640" SDNUM="1033;">2640</TD>
		<TD ALIGN="CENTER" SDVAL="2595" SDNUM="1033;">2595</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_equal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6172" SDNUM="1033;">6172</TD>
		<TD ALIGN="CENTER" SDVAL="2999" SDNUM="1033;">2999</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_equal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="3877" SDNUM="1033;">3877</TD>
		<TD ALIGN="CENTER" SDVAL="2753" SDNUM="1033;">2753</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_notequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2601" SDNUM="1033;">2601</TD>
		<TD ALIGN="CENTER" SDVAL="2875" SDNUM="1033;">2875</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_notequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6445" SDNUM="1033;">6445</TD>
		<TD ALIGN="CENTER" SDVAL="3104" SDNUM="1033;">3104</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_less_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2345" SDNUM="1033;">2345</TD>
		<TD ALIGN="CENTER" SDVAL="2624" SDNUM="1033;">2624</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_less_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6169" SDNUM="1033;">6169</TD>
		<TD ALIGN="CENTER" SDVAL="2874" SDNUM="1033;">2874</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_lessorequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6447" SDNUM="1033;">6447</TD>
		<TD ALIGN="CENTER" SDVAL="3106" SDNUM="1033;">3106</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_lessorequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6422" SDNUM="1033;">6422</TD>
		<TD ALIGN="CENTER" SDVAL="3126" SDNUM="1033;">3126</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_more_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2351" SDNUM="1033;">2351</TD>
		<TD ALIGN="CENTER" SDVAL="2603" SDNUM="1033;">2603</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_more_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2370" SDNUM="1033;">2370</TD>
		<TD ALIGN="CENTER" SDVAL="2630" SDNUM="1033;">2630</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_moreorequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6425" SDNUM="1033;">6425</TD>
		<TD ALIGN="CENTER" SDVAL="3101" SDNUM="1033;">3101</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_moreorequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2624" SDNUM="1033;">2624</TD>
		<TD ALIGN="CENTER" SDVAL="2902" SDNUM="1033;">2902</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_iszero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6167" SDNUM="1033;">6167</TD>
		<TD ALIGN="CENTER" SDVAL="2940" SDNUM="1033;">2940</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_iszero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2353" SDNUM="1033;">2353</TD>
		<TD ALIGN="CENTER" SDVAL="2605" SDNUM="1033;">2605</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_isnotzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2620" SDNUM="1033;">2620</TD>
		<TD ALIGN="CENTER" SDVAL="2879" SDNUM="1033;">2879</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_isnotzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6423" SDNUM="1033;">6423</TD>
		<TD ALIGN="CENTER" SDVAL="3108" SDNUM="1033;">3108</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_lessthanzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2746" SDNUM="1033;">2746</TD>
		<TD ALIGN="CENTER" SDVAL="2754" SDNUM="1033;">2754</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_lessthanzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6170" SDNUM="1033;">6170</TD>
		<TD ALIGN="CENTER" SDVAL="3037" SDNUM="1033;">3037</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_lessorequaltozero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6423" SDNUM="1033;">6423</TD>
		<TD ALIGN="CENTER" SDVAL="3134" SDNUM="1033;">3134</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_lessorequaltozero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6446" SDNUM="1033;">6446</TD>
		<TD ALIGN="CENTER" SDVAL="3133" SDNUM="1033;">3133</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_morethanzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2346" SDNUM="1033;">2346</TD>
		<TD ALIGN="CENTER" SDVAL="2603" SDNUM="1033;">2603</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_morethanzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2345" SDNUM="1033;">2345</TD>
		<TD ALIGN="CENTER" SDVAL="2626" SDNUM="1033;">2626</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_moreorequaltozero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6445" SDNUM="1033;">6445</TD>
		<TD ALIGN="CENTER" SDVAL="3108" SDNUM="1033;">3108</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_moreorequaltozero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2605" SDNUM="1033;">2605</TD>
		<TD ALIGN="CENTER" SDVAL="2878" SDNUM="1033;">2878</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__equal_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1619" SDNUM="1033;">1619</TD>
		<TD ALIGN="CENTER" SDVAL="1591" SDNUM="1033;">1591</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__equal_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1587" SDNUM="1033;">1587</TD>
		<TD ALIGN="CENTER" SDVAL="1620" SDNUM="1033;">1620</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__notequal_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1591" SDNUM="1033;">1591</TD>
		<TD ALIGN="CENTER" SDVAL="1591" SDNUM="1033;">1591</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__notequal_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1652" SDNUM="1033;">1652</TD>
		<TD ALIGN="CENTER" SDVAL="1591" SDNUM="1033;">1591</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__less_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1603" SDNUM="1033;">1603</TD>
		<TD ALIGN="CENTER" SDVAL="1623" SDNUM="1033;">1623</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__less_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1591" SDNUM="1033;">1591</TD>
		<TD ALIGN="CENTER" SDVAL="1593" SDNUM="1033;">1593</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__lessorequal_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1612" SDNUM="1033;">1612</TD>
		<TD ALIGN="CENTER" SDVAL="1594" SDNUM="1033;">1594</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__lessorequal_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1591" SDNUM="1033;">1591</TD>
		<TD ALIGN="CENTER" SDVAL="1625" SDNUM="1033;">1625</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__more_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1597" SDNUM="1033;">1597</TD>
		<TD ALIGN="CENTER" SDVAL="1588" SDNUM="1033;">1588</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__more_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1594" SDNUM="1033;">1594</TD>
		<TD ALIGN="CENTER" SDVAL="1593" SDNUM="1033;">1593</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__moreorequal_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1621" SDNUM="1033;">1621</TD>
		<TD ALIGN="CENTER" SDVAL="1616" SDNUM="1033;">1616</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__moreorequal_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1586" SDNUM="1033;">1586</TD>
		<TD ALIGN="CENTER" SDVAL="1602" SDNUM="1033;">1602</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__iszero_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1590" SDNUM="1033;">1590</TD>
		<TD ALIGN="CENTER" SDVAL="1595" SDNUM="1033;">1595</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__iszero_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1620" SDNUM="1033;">1620</TD>
		<TD ALIGN="CENTER" SDVAL="1590" SDNUM="1033;">1590</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__isnotzero_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1592" SDNUM="1033;">1592</TD>
		<TD ALIGN="CENTER" SDVAL="1619" SDNUM="1033;">1619</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__isnotzero_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1595" SDNUM="1033;">1595</TD>
		<TD ALIGN="CENTER" SDVAL="1595" SDNUM="1033;">1595</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__lessthanzero_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1611" SDNUM="1033;">1611</TD>
		<TD ALIGN="CENTER" SDVAL="1596" SDNUM="1033;">1596</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__lessthanzero_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1591" SDNUM="1033;">1591</TD>
		<TD ALIGN="CENTER" SDVAL="1620" SDNUM="1033;">1620</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__lessorequaltozero_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1591" SDNUM="1033;">1591</TD>
		<TD ALIGN="CENTER" SDVAL="1586" SDNUM="1033;">1586</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__lessorequaltozero_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1619" SDNUM="1033;">1619</TD>
		<TD ALIGN="CENTER" SDVAL="1596" SDNUM="1033;">1596</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__morethanzero_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1592" SDNUM="1033;">1592</TD>
		<TD ALIGN="CENTER" SDVAL="1615" SDNUM="1033;">1615</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__morethanzero_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1589" SDNUM="1033;">1589</TD>
		<TD ALIGN="CENTER" SDVAL="1594" SDNUM="1033;">1594</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__moreorequaltozero_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1616" SDNUM="1033;">1616</TD>
		<TD ALIGN="CENTER" SDVAL="1597" SDNUM="1033;">1597</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__moreorequaltozero_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1590" SDNUM="1033;">1590</TD>
		<TD ALIGN="CENTER" SDVAL="1616" SDNUM="1033;">1616</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_equal_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1597" SDNUM="1033;">1597</TD>
		<TD ALIGN="CENTER" SDVAL="1590" SDNUM="1033;">1590</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_equal_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1620" SDNUM="1033;">1620</TD>
		<TD ALIGN="CENTER" SDVAL="1593" SDNUM="1033;">1593</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_notequal_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1586" SDNUM="1033;">1586</TD>
		<TD ALIGN="CENTER" SDVAL="1620" SDNUM="1033;">1620</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_notequal_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1589" SDNUM="1033;">1589</TD>
		<TD ALIGN="CENTER" SDVAL="1594" SDNUM="1033;">1594</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_less_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1620" SDNUM="1033;">1620</TD>
		<TD ALIGN="CENTER" SDVAL="1591" SDNUM="1033;">1591</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_less_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1594" SDNUM="1033;">1594</TD>
		<TD ALIGN="CENTER" SDVAL="1619" SDNUM="1033;">1619</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_lessorequal_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1593" SDNUM="1033;">1593</TD>
		<TD ALIGN="CENTER" SDVAL="1590" SDNUM="1033;">1590</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_lessorequal_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1611" SDNUM="1033;">1611</TD>
		<TD ALIGN="CENTER" SDVAL="1593" SDNUM="1033;">1593</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_more_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1589" SDNUM="1033;">1589</TD>
		<TD ALIGN="CENTER" SDVAL="1626" SDNUM="1033;">1626</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_more_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1594" SDNUM="1033;">1594</TD>
		<TD ALIGN="CENTER" SDVAL="1587" SDNUM="1033;">1587</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_moreorequal_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1595" SDNUM="1033;">1595</TD>
		<TD ALIGN="CENTER" SDVAL="1595" SDNUM="1033;">1595</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_moreorequal_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1619" SDNUM="1033;">1619</TD>
		<TD ALIGN="CENTER" SDVAL="1622" SDNUM="1033;">1622</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_iszero_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1586" SDNUM="1033;">1586</TD>
		<TD ALIGN="CENTER" SDVAL="1593" SDNUM="1033;">1593</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_iszero_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1593" SDNUM="1033;">1593</TD>
		<TD ALIGN="CENTER" SDVAL="1597" SDNUM="1033;">1597</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_isnotzero_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1617" SDNUM="1033;">1617</TD>
		<TD ALIGN="CENTER" SDVAL="1590" SDNUM="1033;">1590</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_isnotzero_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1595" SDNUM="1033;">1595</TD>
		<TD ALIGN="CENTER" SDVAL="1615" SDNUM="1033;">1615</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_lessthanzero_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1593" SDNUM="1033;">1593</TD>
		<TD ALIGN="CENTER" SDVAL="1592" SDNUM="1033;">1592</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_lessthanzero_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1615" SDNUM="1033;">1615</TD>
		<TD ALIGN="CENTER" SDVAL="1594" SDNUM="1033;">1594</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_lessorequaltozero_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1589" SDNUM="1033;">1589</TD>
		<TD ALIGN="CENTER" SDVAL="1621" SDNUM="1033;">1621</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_lessorequaltozero_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1591" SDNUM="1033;">1591</TD>
		<TD ALIGN="CENTER" SDVAL="1589" SDNUM="1033;">1589</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_morethanzero_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1628" SDNUM="1033;">1628</TD>
		<TD ALIGN="CENTER" SDVAL="1593" SDNUM="1033;">1593</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_morethanzero_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1597" SDNUM="1033;">1597</TD>
		<TD ALIGN="CENTER" SDVAL="1616" SDNUM="1033;">1616</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_moreorequaltozero_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1588" SDNUM="1033;">1588</TD>
		<TD ALIGN="CENTER" SDVAL="1595" SDNUM="1033;">1595</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_moreorequaltozero_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1617" SDNUM="1033;">1617</TD>
		<TD ALIGN="CENTER" SDVAL="1601" SDNUM="1033;">1601</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_equal_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1594" SDNUM="1033;">1594</TD>
		<TD ALIGN="CENTER" SDVAL="1612" SDNUM="1033;">1612</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_equal_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1596" SDNUM="1033;">1596</TD>
		<TD ALIGN="CENTER" SDVAL="1596" SDNUM="1033;">1596</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_notequal_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1618" SDNUM="1033;">1618</TD>
		<TD ALIGN="CENTER" SDVAL="1592" SDNUM="1033;">1592</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_notequal_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1589" SDNUM="1033;">1589</TD>
		<TD ALIGN="CENTER" SDVAL="1626" SDNUM="1033;">1626</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_less_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1591" SDNUM="1033;">1591</TD>
		<TD ALIGN="CENTER" SDVAL="1603" SDNUM="1033;">1603</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_less_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1619" SDNUM="1033;">1619</TD>
		<TD ALIGN="CENTER" SDVAL="1587" SDNUM="1033;">1587</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_lessorequal_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1595" SDNUM="1033;">1595</TD>
		<TD ALIGN="CENTER" SDVAL="1619" SDNUM="1033;">1619</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_lessorequal_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1590" SDNUM="1033;">1590</TD>
		<TD ALIGN="CENTER" SDVAL="1594" SDNUM="1033;">1594</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_more_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1612" SDNUM="1033;">1612</TD>
		<TD ALIGN="CENTER" SDVAL="1595" SDNUM="1033;">1595</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_more_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1591" SDNUM="1033;">1591</TD>
		<TD ALIGN="CENTER" SDVAL="1624" SDNUM="1033;">1624</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_moreorequal_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1590" SDNUM="1033;">1590</TD>
		<TD ALIGN="CENTER" SDVAL="1588" SDNUM="1033;">1588</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_moreorequal_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1599" SDNUM="1033;">1599</TD>
		<TD ALIGN="CENTER" SDVAL="1597" SDNUM="1033;">1597</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_iszero_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1637" SDNUM="1033;">1637</TD>
		<TD ALIGN="CENTER" SDVAL="1619" SDNUM="1033;">1619</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_iszero_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1588" SDNUM="1033;">1588</TD>
		<TD ALIGN="CENTER" SDVAL="1598" SDNUM="1033;">1598</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_isnotzero_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1597" SDNUM="1033;">1597</TD>
		<TD ALIGN="CENTER" SDVAL="1600" SDNUM="1033;">1600</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_isnotzero_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1617" SDNUM="1033;">1617</TD>
		<TD ALIGN="CENTER" SDVAL="1590" SDNUM="1033;">1590</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_lessthanzero_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1597" SDNUM="1033;">1597</TD>
		<TD ALIGN="CENTER" SDVAL="1619" SDNUM="1033;">1619</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_lessthanzero_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1595" SDNUM="1033;">1595</TD>
		<TD ALIGN="CENTER" SDVAL="1592" SDNUM="1033;">1592</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_lessorequaltozero_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1612" SDNUM="1033;">1612</TD>
		<TD ALIGN="CENTER" SDVAL="1593" SDNUM="1033;">1593</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_lessorequaltozero_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1590" SDNUM="1033;">1590</TD>
		<TD ALIGN="CENTER" SDVAL="1625" SDNUM="1033;">1625</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_morethanzero_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1594" SDNUM="1033;">1594</TD>
		<TD ALIGN="CENTER" SDVAL="1588" SDNUM="1033;">1588</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_morethanzero_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1620" SDNUM="1033;">1620</TD>
		<TD ALIGN="CENTER" SDVAL="1596" SDNUM="1033;">1596</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_moreorequaltozero_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="1591" SDNUM="1033;">1591</TD>
		<TD ALIGN="CENTER" SDVAL="1619" SDNUM="1033;">1619</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_moreorequaltozero_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="1589" SDNUM="1033;">1589</TD>
		<TD ALIGN="CENTER" SDVAL="1598" SDNUM="1033;">1598</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_equal_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2119" SDNUM="1033;">2119</TD>
		<TD ALIGN="CENTER" SDVAL="2098" SDNUM="1033;">2098</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_equal_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2100" SDNUM="1033;">2100</TD>
		<TD ALIGN="CENTER" SDVAL="2120" SDNUM="1033;">2120</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_notequal_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2123" SDNUM="1033;">2123</TD>
		<TD ALIGN="CENTER" SDVAL="2096" SDNUM="1033;">2096</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_notequal_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2094" SDNUM="1033;">2094</TD>
		<TD ALIGN="CENTER" SDVAL="2121" SDNUM="1033;">2121</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_less_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2096" SDNUM="1033;">2096</TD>
		<TD ALIGN="CENTER" SDVAL="2095" SDNUM="1033;">2095</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_less_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2120" SDNUM="1033;">2120</TD>
		<TD ALIGN="CENTER" SDVAL="2125" SDNUM="1033;">2125</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_lessorequal_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2095" SDNUM="1033;">2095</TD>
		<TD ALIGN="CENTER" SDVAL="2095" SDNUM="1033;">2095</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_lessorequal_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2124" SDNUM="1033;">2124</TD>
		<TD ALIGN="CENTER" SDVAL="2096" SDNUM="1033;">2096</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_more_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2099" SDNUM="1033;">2099</TD>
		<TD ALIGN="CENTER" SDVAL="2120" SDNUM="1033;">2120</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_more_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2126" SDNUM="1033;">2126</TD>
		<TD ALIGN="CENTER" SDVAL="2100" SDNUM="1033;">2100</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_moreorequal_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2097" SDNUM="1033;">2097</TD>
		<TD ALIGN="CENTER" SDVAL="2120" SDNUM="1033;">2120</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_moreorequal_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2095" SDNUM="1033;">2095</TD>
		<TD ALIGN="CENTER" SDVAL="2098" SDNUM="1033;">2098</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_iszero_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2123" SDNUM="1033;">2123</TD>
		<TD ALIGN="CENTER" SDVAL="2120" SDNUM="1033;">2120</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_iszero_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2095" SDNUM="1033;">2095</TD>
		<TD ALIGN="CENTER" SDVAL="2104" SDNUM="1033;">2104</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_isnotzero_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2120" SDNUM="1033;">2120</TD>
		<TD ALIGN="CENTER" SDVAL="2106" SDNUM="1033;">2106</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_isnotzero_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2094" SDNUM="1033;">2094</TD>
		<TD ALIGN="CENTER" SDVAL="2120" SDNUM="1033;">2120</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_lessthanzero_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2097" SDNUM="1033;">2097</TD>
		<TD ALIGN="CENTER" SDVAL="2095" SDNUM="1033;">2095</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_lessthanzero_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2126" SDNUM="1033;">2126</TD>
		<TD ALIGN="CENTER" SDVAL="2122" SDNUM="1033;">2122</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_lessorequaltozero_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2096" SDNUM="1033;">2096</TD>
		<TD ALIGN="CENTER" SDVAL="2095" SDNUM="1033;">2095</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_lessorequaltozero_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2124" SDNUM="1033;">2124</TD>
		<TD ALIGN="CENTER" SDVAL="2099" SDNUM="1033;">2099</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_morethanzero_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2097" SDNUM="1033;">2097</TD>
		<TD ALIGN="CENTER" SDVAL="2123" SDNUM="1033;">2123</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_morethanzero_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2124" SDNUM="1033;">2124</TD>
		<TD ALIGN="CENTER" SDVAL="2096" SDNUM="1033;">2096</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_moreorequaltozero_inline(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2096" SDNUM="1033;">2096</TD>
		<TD ALIGN="CENTER" SDVAL="2122" SDNUM="1033;">2122</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_moreorequaltozero_inline(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2095" SDNUM="1033;">2095</TD>
		<TD ALIGN="CENTER" SDVAL="2098" SDNUM="1033;">2098</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="16" ALIGN="LEFT">Elapsed time:</TD>
		<TD ALIGN="CENTER" SDVAL="1025791" SDNUM="1033;">1025791</TD>
		<TD ALIGN="CENTER" SDVAL="875774" SDNUM="1033;">875774</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="16" ALIGN="LEFT"><BR></TD>
		<TD ALIGN="CENTER"><BR></TD>
		<TD ALIGN="CENTER"><BR></TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD COLSPAN=3 HEIGHT="17" ALIGN="LEFT">&ldquo;Nop&rdquo; inserted takes ~85% the time needed of original(not patched)</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
</TABLE>
<!-- ************************************************************************** -->
<HR>
<A NAME="table2"><H1>Sheet 3: <EM>Step II</EM></H1></A>
<TABLE CELLSPACING="0" COLS="4" BORDER="0">
	<COLGROUP WIDTH="296"></COLGROUP>
	<COLGROUP WIDTH="86"></COLGROUP>
	<COLGROUP WIDTH="116"></COLGROUP>
	<COLGROUP WIDTH="85"></COLGROUP>
	<TR>
		<TD COLSPAN=6 HEIGHT="17" ALIGN="LEFT">Due to the fact that inlined functions are not inserted with &ldquo;nop&rdquo;s they have been removed from the analysis.</TD>
		</TR>
	<TR>
		<TD HEIGHT="16" ALIGN="LEFT"><BR></TD>
		<TD ALIGN="LEFT"><BR></TD>
		<TD ALIGN="LEFT"><BR></TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT"><BR></TD>
		<TD ALIGN="CENTER">Original[ms]</TD>
		<TD ALIGN="CENTER">NOPInserted[ms]</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__equal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2567" SDNUM="1033;">2567</TD>
		<TD ALIGN="CENTER" SDVAL="2573" SDNUM="1033;">2573</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__equal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2794" SDNUM="1033;">2794</TD>
		<TD ALIGN="CENTER" SDVAL="2808" SDNUM="1033;">2808</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__notequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2699" SDNUM="1033;">2699</TD>
		<TD ALIGN="CENTER" SDVAL="3141" SDNUM="1033;">3141</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__notequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2481" SDNUM="1033;">2481</TD>
		<TD ALIGN="CENTER" SDVAL="3061" SDNUM="1033;">3061</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__less_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2820" SDNUM="1033;">2820</TD>
		<TD ALIGN="CENTER" SDVAL="2827" SDNUM="1033;">2827</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__less_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2549" SDNUM="1033;">2549</TD>
		<TD ALIGN="CENTER" SDVAL="2558" SDNUM="1033;">2558</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__lessorequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2309" SDNUM="1033;">2309</TD>
		<TD ALIGN="CENTER" SDVAL="2320" SDNUM="1033;">2320</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__lessorequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2293" SDNUM="1033;">2293</TD>
		<TD ALIGN="CENTER" SDVAL="2293" SDNUM="1033;">2293</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__more_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2819" SDNUM="1033;">2819</TD>
		<TD ALIGN="CENTER" SDVAL="2830" SDNUM="1033;">2830</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__more_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2796" SDNUM="1033;">2796</TD>
		<TD ALIGN="CENTER" SDVAL="2807" SDNUM="1033;">2807</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__moreorequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2313" SDNUM="1033;">2313</TD>
		<TD ALIGN="CENTER" SDVAL="2316" SDNUM="1033;">2316</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__moreorequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2540" SDNUM="1033;">2540</TD>
		<TD ALIGN="CENTER" SDVAL="2547" SDNUM="1033;">2547</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__iszero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2573" SDNUM="1033;">2573</TD>
		<TD ALIGN="CENTER" SDVAL="2571" SDNUM="1033;">2571</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__iszero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2825" SDNUM="1033;">2825</TD>
		<TD ALIGN="CENTER" SDVAL="2805" SDNUM="1033;">2805</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__isnotzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2540" SDNUM="1033;">2540</TD>
		<TD ALIGN="CENTER" SDVAL="2570" SDNUM="1033;">2570</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__isnotzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2303" SDNUM="1033;">2303</TD>
		<TD ALIGN="CENTER" SDVAL="2298" SDNUM="1033;">2298</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__lessthanzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2812" SDNUM="1033;">2812</TD>
		<TD ALIGN="CENTER" SDVAL="2828" SDNUM="1033;">2828</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__lessthanzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2570" SDNUM="1033;">2570</TD>
		<TD ALIGN="CENTER" SDVAL="2576" SDNUM="1033;">2576</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__lessorequaltozero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2291" SDNUM="1033;">2291</TD>
		<TD ALIGN="CENTER" SDVAL="5758" SDNUM="1033;">5758</TD>
		<TD ALIGN="LEFT">*</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__lessorequaltozero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2287" SDNUM="1033;">2287</TD>
		<TD ALIGN="CENTER" SDVAL="5762" SDNUM="1033;">5762</TD>
		<TD ALIGN="LEFT">*</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__morethanzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2828" SDNUM="1033;">2828</TD>
		<TD ALIGN="CENTER" SDVAL="2790" SDNUM="1033;">2790</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__morethanzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2822" SDNUM="1033;">2822</TD>
		<TD ALIGN="CENTER" SDVAL="2822" SDNUM="1033;">2822</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__moreorequaltozero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2285" SDNUM="1033;">2285</TD>
		<TD ALIGN="CENTER" SDVAL="2284" SDNUM="1033;">2284</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__moreorequaltozero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2574" SDNUM="1033;">2574</TD>
		<TD ALIGN="CENTER" SDVAL="2563" SDNUM="1033;">2563</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_equal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6123" SDNUM="1033;">6123</TD>
		<TD ALIGN="CENTER" SDVAL="2542" SDNUM="1033;">2542</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_equal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2795" SDNUM="1033;">2795</TD>
		<TD ALIGN="CENTER" SDVAL="2821" SDNUM="1033;">2821</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_notequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2821" SDNUM="1033;">2821</TD>
		<TD ALIGN="CENTER" SDVAL="2816" SDNUM="1033;">2816</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_notequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6127" SDNUM="1033;">6127</TD>
		<TD ALIGN="CENTER" SDVAL="2597" SDNUM="1033;">2597</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_less_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2820" SDNUM="1033;">2820</TD>
		<TD ALIGN="CENTER" SDVAL="2822" SDNUM="1033;">2822</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_less_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6159" SDNUM="1033;">6159</TD>
		<TD ALIGN="CENTER" SDVAL="2613" SDNUM="1033;">2613</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_lessorequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6126" SDNUM="1033;">6126</TD>
		<TD ALIGN="CENTER" SDVAL="2568" SDNUM="1033;">2568</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_lessorequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6127" SDNUM="1033;">6127</TD>
		<TD ALIGN="CENTER" SDVAL="2544" SDNUM="1033;">2544</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_more_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2825" SDNUM="1033;">2825</TD>
		<TD ALIGN="CENTER" SDVAL="2818" SDNUM="1033;">2818</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_more_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2819" SDNUM="1033;">2819</TD>
		<TD ALIGN="CENTER" SDVAL="2790" SDNUM="1033;">2790</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_moreorequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6121" SDNUM="1033;">6121</TD>
		<TD ALIGN="CENTER" SDVAL="2568" SDNUM="1033;">2568</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_moreorequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2792" SDNUM="1033;">2792</TD>
		<TD ALIGN="CENTER" SDVAL="2792" SDNUM="1033;">2792</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_iszero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6154" SDNUM="1033;">6154</TD>
		<TD ALIGN="CENTER" SDVAL="2566" SDNUM="1033;">2566</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_iszero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2793" SDNUM="1033;">2793</TD>
		<TD ALIGN="CENTER" SDVAL="2796" SDNUM="1033;">2796</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_isnotzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2820" SDNUM="1033;">2820</TD>
		<TD ALIGN="CENTER" SDVAL="2815" SDNUM="1033;">2815</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_isnotzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6144" SDNUM="1033;">6144</TD>
		<TD ALIGN="CENTER" SDVAL="2573" SDNUM="1033;">2573</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_lessthanzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2800" SDNUM="1033;">2800</TD>
		<TD ALIGN="CENTER" SDVAL="2793" SDNUM="1033;">2793</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_lessthanzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6175" SDNUM="1033;">6175</TD>
		<TD ALIGN="CENTER" SDVAL="2568" SDNUM="1033;">2568</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_lessorequaltozero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6182" SDNUM="1033;">6182</TD>
		<TD ALIGN="CENTER" SDVAL="2601" SDNUM="1033;">2601</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_lessorequaltozero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6186" SDNUM="1033;">6186</TD>
		<TD ALIGN="CENTER" SDVAL="2632" SDNUM="1033;">2632</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_morethanzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2879" SDNUM="1033;">2879</TD>
		<TD ALIGN="CENTER" SDVAL="2853" SDNUM="1033;">2853</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_morethanzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2846" SDNUM="1033;">2846</TD>
		<TD ALIGN="CENTER" SDVAL="2883" SDNUM="1033;">2883</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_moreorequaltozero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6201" SDNUM="1033;">6201</TD>
		<TD ALIGN="CENTER" SDVAL="2601" SDNUM="1033;">2601</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_moreorequaltozero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2846" SDNUM="1033;">2846</TD>
		<TD ALIGN="CENTER" SDVAL="2882" SDNUM="1033;">2882</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_equal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2628" SDNUM="1033;">2628</TD>
		<TD ALIGN="CENTER" SDVAL="2608" SDNUM="1033;">2608</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_equal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2846" SDNUM="1033;">2846</TD>
		<TD ALIGN="CENTER" SDVAL="2880" SDNUM="1033;">2880</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_notequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2625" SDNUM="1033;">2625</TD>
		<TD ALIGN="CENTER" SDVAL="2627" SDNUM="1033;">2627</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_notequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2345" SDNUM="1033;">2345</TD>
		<TD ALIGN="CENTER" SDVAL="2358" SDNUM="1033;">2358</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_less_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2875" SDNUM="1033;">2875</TD>
		<TD ALIGN="CENTER" SDVAL="2881" SDNUM="1033;">2881</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_less_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2601" SDNUM="1033;">2601</TD>
		<TD ALIGN="CENTER" SDVAL="2604" SDNUM="1033;">2604</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_lessorequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2373" SDNUM="1033;">2373</TD>
		<TD ALIGN="CENTER" SDVAL="2387" SDNUM="1033;">2387</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_lessorequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2346" SDNUM="1033;">2346</TD>
		<TD ALIGN="CENTER" SDVAL="2348" SDNUM="1033;">2348</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_more_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2871" SDNUM="1033;">2871</TD>
		<TD ALIGN="CENTER" SDVAL="2881" SDNUM="1033;">2881</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_more_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2856" SDNUM="1033;">2856</TD>
		<TD ALIGN="CENTER" SDVAL="2860" SDNUM="1033;">2860</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_moreorequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="3009" SDNUM="1033;">3009</TD>
		<TD ALIGN="CENTER" SDVAL="2998" SDNUM="1033;">2998</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_moreorequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="3027" SDNUM="1033;">3027</TD>
		<TD ALIGN="CENTER" SDVAL="3270" SDNUM="1033;">3270</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_iszero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2597" SDNUM="1033;">2597</TD>
		<TD ALIGN="CENTER" SDVAL="2630" SDNUM="1033;">2630</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_iszero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2875" SDNUM="1033;">2875</TD>
		<TD ALIGN="CENTER" SDVAL="2883" SDNUM="1033;">2883</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_isnotzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2602" SDNUM="1033;">2602</TD>
		<TD ALIGN="CENTER" SDVAL="2602" SDNUM="1033;">2602</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_isnotzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2372" SDNUM="1033;">2372</TD>
		<TD ALIGN="CENTER" SDVAL="2377" SDNUM="1033;">2377</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_lessthanzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2853" SDNUM="1033;">2853</TD>
		<TD ALIGN="CENTER" SDVAL="2857" SDNUM="1033;">2857</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_lessthanzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2629" SDNUM="1033;">2629</TD>
		<TD ALIGN="CENTER" SDVAL="2634" SDNUM="1033;">2634</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_lessorequaltozero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2345" SDNUM="1033;">2345</TD>
		<TD ALIGN="CENTER" SDVAL="2351" SDNUM="1033;">2351</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_lessorequaltozero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2367" SDNUM="1033;">2367</TD>
		<TD ALIGN="CENTER" SDVAL="2377" SDNUM="1033;">2377</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_morethanzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2851" SDNUM="1033;">2851</TD>
		<TD ALIGN="CENTER" SDVAL="2860" SDNUM="1033;">2860</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_morethanzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2886" SDNUM="1033;">2886</TD>
		<TD ALIGN="CENTER" SDVAL="2883" SDNUM="1033;">2883</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_moreorequaltozero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2343" SDNUM="1033;">2343</TD>
		<TD ALIGN="CENTER" SDVAL="2356" SDNUM="1033;">2356</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_moreorequaltozero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2625" SDNUM="1033;">2625</TD>
		<TD ALIGN="CENTER" SDVAL="2629" SDNUM="1033;">2629</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_equal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6170" SDNUM="1033;">6170</TD>
		<TD ALIGN="CENTER" SDVAL="2608" SDNUM="1033;">2608</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_equal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2881" SDNUM="1033;">2881</TD>
		<TD ALIGN="CENTER" SDVAL="2882" SDNUM="1033;">2882</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_notequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2849" SDNUM="1033;">2849</TD>
		<TD ALIGN="CENTER" SDVAL="2862" SDNUM="1033;">2862</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_notequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6171" SDNUM="1033;">6171</TD>
		<TD ALIGN="CENTER" SDVAL="2629" SDNUM="1033;">2629</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_less_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2878" SDNUM="1033;">2878</TD>
		<TD ALIGN="CENTER" SDVAL="2884" SDNUM="1033;">2884</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_less_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6171" SDNUM="1033;">6171</TD>
		<TD ALIGN="CENTER" SDVAL="2611" SDNUM="1033;">2611</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_lessorequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6193" SDNUM="1033;">6193</TD>
		<TD ALIGN="CENTER" SDVAL="2634" SDNUM="1033;">2634</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_lessorequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6172" SDNUM="1033;">6172</TD>
		<TD ALIGN="CENTER" SDVAL="2604" SDNUM="1033;">2604</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_more_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2857" SDNUM="1033;">2857</TD>
		<TD ALIGN="CENTER" SDVAL="2890" SDNUM="1033;">2890</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_more_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2876" SDNUM="1033;">2876</TD>
		<TD ALIGN="CENTER" SDVAL="2859" SDNUM="1033;">2859</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_moreorequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6169" SDNUM="1033;">6169</TD>
		<TD ALIGN="CENTER" SDVAL="2633" SDNUM="1033;">2633</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_moreorequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2876" SDNUM="1033;">2876</TD>
		<TD ALIGN="CENTER" SDVAL="2858" SDNUM="1033;">2858</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_iszero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6179" SDNUM="1033;">6179</TD>
		<TD ALIGN="CENTER" SDVAL="2630" SDNUM="1033;">2630</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_iszero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2877" SDNUM="1033;">2877</TD>
		<TD ALIGN="CENTER" SDVAL="2864" SDNUM="1033;">2864</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_isnotzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2850" SDNUM="1033;">2850</TD>
		<TD ALIGN="CENTER" SDVAL="2883" SDNUM="1033;">2883</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_isnotzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6186" SDNUM="1033;">6186</TD>
		<TD ALIGN="CENTER" SDVAL="2631" SDNUM="1033;">2631</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_lessthanzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2875" SDNUM="1033;">2875</TD>
		<TD ALIGN="CENTER" SDVAL="2862" SDNUM="1033;">2862</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_lessthanzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6169" SDNUM="1033;">6169</TD>
		<TD ALIGN="CENTER" SDVAL="2632" SDNUM="1033;">2632</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_lessorequaltozero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6170" SDNUM="1033;">6170</TD>
		<TD ALIGN="CENTER" SDVAL="2609" SDNUM="1033;">2609</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_lessorequaltozero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6193" SDNUM="1033;">6193</TD>
		<TD ALIGN="CENTER" SDVAL="2629" SDNUM="1033;">2629</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_morethanzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2857" SDNUM="1033;">2857</TD>
		<TD ALIGN="CENTER" SDVAL="2862" SDNUM="1033;">2862</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_morethanzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2874" SDNUM="1033;">2874</TD>
		<TD ALIGN="CENTER" SDVAL="2889" SDNUM="1033;">2889</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_moreorequaltozero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6175" SDNUM="1033;">6175</TD>
		<TD ALIGN="CENTER" SDVAL="2604" SDNUM="1033;">2604</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_constref_moreorequaltozero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2898" SDNUM="1033;">2898</TD>
		<TD ALIGN="CENTER" SDVAL="2903" SDNUM="1033;">2903</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="16" ALIGN="LEFT">int64__equal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2601" SDNUM="1033;">2601</TD>
		<TD ALIGN="CENTER" SDVAL="2625" SDNUM="1033;">2625</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="16" ALIGN="LEFT">int64__equal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2375" SDNUM="1033;">2375</TD>
		<TD ALIGN="CENTER" SDVAL="2349" SDNUM="1033;">2349</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__notequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2600" SDNUM="1033;">2600</TD>
		<TD ALIGN="CENTER" SDVAL="2626" SDNUM="1033;">2626</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__notequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2885" SDNUM="1033;">2885</TD>
		<TD ALIGN="CENTER" SDVAL="2859" SDNUM="1033;">2859</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="16" ALIGN="LEFT">int64__less_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2345" SDNUM="1033;">2345</TD>
		<TD ALIGN="CENTER" SDVAL="2370" SDNUM="1033;">2370</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="16" ALIGN="LEFT">int64__less_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2628" SDNUM="1033;">2628</TD>
		<TD ALIGN="CENTER" SDVAL="2604" SDNUM="1033;">2604</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__lessorequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2856" SDNUM="1033;">2856</TD>
		<TD ALIGN="CENTER" SDVAL="2881" SDNUM="1033;">2881</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__lessorequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2878" SDNUM="1033;">2878</TD>
		<TD ALIGN="CENTER" SDVAL="2854" SDNUM="1033;">2854</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="16" ALIGN="LEFT">int64__more_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2545" SDNUM="1033;">2545</TD>
		<TD ALIGN="CENTER" SDVAL="2375" SDNUM="1033;">2375</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="16" ALIGN="LEFT">int64__more_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2418" SDNUM="1033;">2418</TD>
		<TD ALIGN="CENTER" SDVAL="2522" SDNUM="1033;">2522</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__moreorequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2897" SDNUM="1033;">2897</TD>
		<TD ALIGN="CENTER" SDVAL="2896" SDNUM="1033;">2896</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__moreorequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2606" SDNUM="1033;">2606</TD>
		<TD ALIGN="CENTER" SDVAL="2631" SDNUM="1033;">2631</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__iszero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2630" SDNUM="1033;">2630</TD>
		<TD ALIGN="CENTER" SDVAL="2603" SDNUM="1033;">2603</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__iszero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2346" SDNUM="1033;">2346</TD>
		<TD ALIGN="CENTER" SDVAL="2349" SDNUM="1033;">2349</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__isnotzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2625" SDNUM="1033;">2625</TD>
		<TD ALIGN="CENTER" SDVAL="2624" SDNUM="1033;">2624</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__isnotzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2858" SDNUM="1033;">2858</TD>
		<TD ALIGN="CENTER" SDVAL="2883" SDNUM="1033;">2883</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__lessthanzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2370" SDNUM="1033;">2370</TD>
		<TD ALIGN="CENTER" SDVAL="2347" SDNUM="1033;">2347</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__lessthanzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2598" SDNUM="1033;">2598</TD>
		<TD ALIGN="CENTER" SDVAL="2622" SDNUM="1033;">2622</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__lessorequaltozero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2879" SDNUM="1033;">2879</TD>
		<TD ALIGN="CENTER" SDVAL="2854" SDNUM="1033;">2854</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__lessorequaltozero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2851" SDNUM="1033;">2851</TD>
		<TD ALIGN="CENTER" SDVAL="2877" SDNUM="1033;">2877</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__morethanzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2371" SDNUM="1033;">2371</TD>
		<TD ALIGN="CENTER" SDVAL="2351" SDNUM="1033;">2351</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__morethanzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2349" SDNUM="1033;">2349</TD>
		<TD ALIGN="CENTER" SDVAL="2371" SDNUM="1033;">2371</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__moreorequaltozero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2878" SDNUM="1033;">2878</TD>
		<TD ALIGN="CENTER" SDVAL="2854" SDNUM="1033;">2854</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__moreorequaltozero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2600" SDNUM="1033;">2600</TD>
		<TD ALIGN="CENTER" SDVAL="2625" SDNUM="1033;">2625</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="16" ALIGN="LEFT">int64_var_equal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6192" SDNUM="1033;">6192</TD>
		<TD ALIGN="CENTER" SDVAL="3114" SDNUM="1033;">3114</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="16" ALIGN="LEFT">int64_var_equal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2528" SDNUM="1033;">2528</TD>
		<TD ALIGN="CENTER" SDVAL="2888" SDNUM="1033;">2888</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_notequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2625" SDNUM="1033;">2625</TD>
		<TD ALIGN="CENTER" SDVAL="2877" SDNUM="1033;">2877</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_notequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6422" SDNUM="1033;">6422</TD>
		<TD ALIGN="CENTER" SDVAL="3105" SDNUM="1033;">3105</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="16" ALIGN="LEFT">int64_var_less_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2346" SDNUM="1033;">2346</TD>
		<TD ALIGN="CENTER" SDVAL="2622" SDNUM="1033;">2622</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="16" ALIGN="LEFT">int64_var_less_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6192" SDNUM="1033;">6192</TD>
		<TD ALIGN="CENTER" SDVAL="2852" SDNUM="1033;">2852</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_lessorequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6429" SDNUM="1033;">6429</TD>
		<TD ALIGN="CENTER" SDVAL="3132" SDNUM="1033;">3132</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_lessorequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6424" SDNUM="1033;">6424</TD>
		<TD ALIGN="CENTER" SDVAL="3129" SDNUM="1033;">3129</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="16" ALIGN="LEFT">int64_var_more_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2366" SDNUM="1033;">2366</TD>
		<TD ALIGN="CENTER" SDVAL="2597" SDNUM="1033;">2597</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="16" ALIGN="LEFT">int64_var_more_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2345" SDNUM="1033;">2345</TD>
		<TD ALIGN="CENTER" SDVAL="2625" SDNUM="1033;">2625</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_moreorequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6421" SDNUM="1033;">6421</TD>
		<TD ALIGN="CENTER" SDVAL="3105" SDNUM="1033;">3105</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_moreorequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2627" SDNUM="1033;">2627</TD>
		<TD ALIGN="CENTER" SDVAL="2883" SDNUM="1033;">2883</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_iszero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6169" SDNUM="1033;">6169</TD>
		<TD ALIGN="CENTER" SDVAL="2850" SDNUM="1033;">2850</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_iszero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2366" SDNUM="1033;">2366</TD>
		<TD ALIGN="CENTER" SDVAL="2620" SDNUM="1033;">2620</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_isnotzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2595" SDNUM="1033;">2595</TD>
		<TD ALIGN="CENTER" SDVAL="2854" SDNUM="1033;">2854</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_isnotzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6419" SDNUM="1033;">6419</TD>
		<TD ALIGN="CENTER" SDVAL="3125" SDNUM="1033;">3125</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_lessthanzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="5827" SDNUM="1033;">5827</TD>
		<TD ALIGN="CENTER" SDVAL="4066" SDNUM="1033;">4066</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_lessthanzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6167" SDNUM="1033;">6167</TD>
		<TD ALIGN="CENTER" SDVAL="5619" SDNUM="1033;">5619</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_lessorequaltozero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6422" SDNUM="1033;">6422</TD>
		<TD ALIGN="CENTER" SDVAL="3128" SDNUM="1033;">3128</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_lessorequaltozero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6426" SDNUM="1033;">6426</TD>
		<TD ALIGN="CENTER" SDVAL="3100" SDNUM="1033;">3100</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_morethanzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2367" SDNUM="1033;">2367</TD>
		<TD ALIGN="CENTER" SDVAL="2623" SDNUM="1033;">2623</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_morethanzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2340" SDNUM="1033;">2340</TD>
		<TD ALIGN="CENTER" SDVAL="2593" SDNUM="1033;">2593</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_moreorequaltozero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6444" SDNUM="1033;">6444</TD>
		<TD ALIGN="CENTER" SDVAL="3128" SDNUM="1033;">3128</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_moreorequaltozero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2599" SDNUM="1033;">2599</TD>
		<TD ALIGN="CENTER" SDVAL="2850" SDNUM="1033;">2850</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_equal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2622" SDNUM="1033;">2622</TD>
		<TD ALIGN="CENTER" SDVAL="2622" SDNUM="1033;">2622</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_equal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2343" SDNUM="1033;">2343</TD>
		<TD ALIGN="CENTER" SDVAL="2339" SDNUM="1033;">2339</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_notequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2623" SDNUM="1033;">2623</TD>
		<TD ALIGN="CENTER" SDVAL="2629" SDNUM="1033;">2629</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_notequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2850" SDNUM="1033;">2850</TD>
		<TD ALIGN="CENTER" SDVAL="2871" SDNUM="1033;">2871</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_less_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2370" SDNUM="1033;">2370</TD>
		<TD ALIGN="CENTER" SDVAL="2343" SDNUM="1033;">2343</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_less_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2594" SDNUM="1033;">2594</TD>
		<TD ALIGN="CENTER" SDVAL="2626" SDNUM="1033;">2626</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_lessorequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2879" SDNUM="1033;">2879</TD>
		<TD ALIGN="CENTER" SDVAL="2849" SDNUM="1033;">2849</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_lessorequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2849" SDNUM="1033;">2849</TD>
		<TD ALIGN="CENTER" SDVAL="2873" SDNUM="1033;">2873</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_more_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2547" SDNUM="1033;">2547</TD>
		<TD ALIGN="CENTER" SDVAL="2520" SDNUM="1033;">2520</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_more_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2526" SDNUM="1033;">2526</TD>
		<TD ALIGN="CENTER" SDVAL="2554" SDNUM="1033;">2554</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_moreorequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2870" SDNUM="1033;">2870</TD>
		<TD ALIGN="CENTER" SDVAL="2847" SDNUM="1033;">2847</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_moreorequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2624" SDNUM="1033;">2624</TD>
		<TD ALIGN="CENTER" SDVAL="2628" SDNUM="1033;">2628</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_iszero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2600" SDNUM="1033;">2600</TD>
		<TD ALIGN="CENTER" SDVAL="2595" SDNUM="1033;">2595</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_iszero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2368" SDNUM="1033;">2368</TD>
		<TD ALIGN="CENTER" SDVAL="2370" SDNUM="1033;">2370</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_isnotzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2595" SDNUM="1033;">2595</TD>
		<TD ALIGN="CENTER" SDVAL="2599" SDNUM="1033;">2599</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_isnotzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2879" SDNUM="1033;">2879</TD>
		<TD ALIGN="CENTER" SDVAL="2878" SDNUM="1033;">2878</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_lessthanzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2340" SDNUM="1033;">2340</TD>
		<TD ALIGN="CENTER" SDVAL="2342" SDNUM="1033;">2342</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_lessthanzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2619" SDNUM="1033;">2619</TD>
		<TD ALIGN="CENTER" SDVAL="2620" SDNUM="1033;">2620</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_lessorequaltozero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2860" SDNUM="1033;">2860</TD>
		<TD ALIGN="CENTER" SDVAL="2852" SDNUM="1033;">2852</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_lessorequaltozero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2874" SDNUM="1033;">2874</TD>
		<TD ALIGN="CENTER" SDVAL="2875" SDNUM="1033;">2875</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_morethanzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2345" SDNUM="1033;">2345</TD>
		<TD ALIGN="CENTER" SDVAL="2370" SDNUM="1033;">2370</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_morethanzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2366" SDNUM="1033;">2366</TD>
		<TD ALIGN="CENTER" SDVAL="2346" SDNUM="1033;">2346</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_moreorequaltozero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2853" SDNUM="1033;">2853</TD>
		<TD ALIGN="CENTER" SDVAL="2875" SDNUM="1033;">2875</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_moreorequaltozero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2640" SDNUM="1033;">2640</TD>
		<TD ALIGN="CENTER" SDVAL="2595" SDNUM="1033;">2595</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_equal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6172" SDNUM="1033;">6172</TD>
		<TD ALIGN="CENTER" SDVAL="2999" SDNUM="1033;">2999</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_equal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="3877" SDNUM="1033;">3877</TD>
		<TD ALIGN="CENTER" SDVAL="2753" SDNUM="1033;">2753</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_notequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2601" SDNUM="1033;">2601</TD>
		<TD ALIGN="CENTER" SDVAL="2875" SDNUM="1033;">2875</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_notequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6445" SDNUM="1033;">6445</TD>
		<TD ALIGN="CENTER" SDVAL="3104" SDNUM="1033;">3104</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_less_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2345" SDNUM="1033;">2345</TD>
		<TD ALIGN="CENTER" SDVAL="2624" SDNUM="1033;">2624</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_less_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6169" SDNUM="1033;">6169</TD>
		<TD ALIGN="CENTER" SDVAL="2874" SDNUM="1033;">2874</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_lessorequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6447" SDNUM="1033;">6447</TD>
		<TD ALIGN="CENTER" SDVAL="3106" SDNUM="1033;">3106</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_lessorequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6422" SDNUM="1033;">6422</TD>
		<TD ALIGN="CENTER" SDVAL="3126" SDNUM="1033;">3126</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_more_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2351" SDNUM="1033;">2351</TD>
		<TD ALIGN="CENTER" SDVAL="2603" SDNUM="1033;">2603</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_more_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2370" SDNUM="1033;">2370</TD>
		<TD ALIGN="CENTER" SDVAL="2630" SDNUM="1033;">2630</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_moreorequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6425" SDNUM="1033;">6425</TD>
		<TD ALIGN="CENTER" SDVAL="3101" SDNUM="1033;">3101</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_moreorequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2624" SDNUM="1033;">2624</TD>
		<TD ALIGN="CENTER" SDVAL="2902" SDNUM="1033;">2902</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_iszero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6167" SDNUM="1033;">6167</TD>
		<TD ALIGN="CENTER" SDVAL="2940" SDNUM="1033;">2940</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_iszero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2353" SDNUM="1033;">2353</TD>
		<TD ALIGN="CENTER" SDVAL="2605" SDNUM="1033;">2605</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_isnotzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2620" SDNUM="1033;">2620</TD>
		<TD ALIGN="CENTER" SDVAL="2879" SDNUM="1033;">2879</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_isnotzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6423" SDNUM="1033;">6423</TD>
		<TD ALIGN="CENTER" SDVAL="3108" SDNUM="1033;">3108</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_lessthanzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2746" SDNUM="1033;">2746</TD>
		<TD ALIGN="CENTER" SDVAL="2754" SDNUM="1033;">2754</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_lessthanzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6170" SDNUM="1033;">6170</TD>
		<TD ALIGN="CENTER" SDVAL="3037" SDNUM="1033;">3037</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_lessorequaltozero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6423" SDNUM="1033;">6423</TD>
		<TD ALIGN="CENTER" SDVAL="3134" SDNUM="1033;">3134</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_lessorequaltozero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6446" SDNUM="1033;">6446</TD>
		<TD ALIGN="CENTER" SDVAL="3133" SDNUM="1033;">3133</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_morethanzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2346" SDNUM="1033;">2346</TD>
		<TD ALIGN="CENTER" SDVAL="2603" SDNUM="1033;">2603</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_morethanzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2345" SDNUM="1033;">2345</TD>
		<TD ALIGN="CENTER" SDVAL="2626" SDNUM="1033;">2626</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_moreorequaltozero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6445" SDNUM="1033;">6445</TD>
		<TD ALIGN="CENTER" SDVAL="3108" SDNUM="1033;">3108</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_constref_moreorequaltozero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2605" SDNUM="1033;">2605</TD>
		<TD ALIGN="CENTER" SDVAL="2878" SDNUM="1033;">2878</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="16" ALIGN="LEFT">Elapsed time:</TD>
		<TD ALIGN="CENTER" SDVAL="684104" SDNUM="1033;">684104</TD>
		<TD ALIGN="CENTER" SDVAL="533612" SDNUM="1033;">533612</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="16" ALIGN="LEFT"><BR></TD>
		<TD ALIGN="LEFT"><BR></TD>
		<TD ALIGN="LEFT"><BR></TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD COLSPAN=4 HEIGHT="17" ALIGN="LEFT">&ldquo;Nop&rdquo; inserted takes ~78% the time needed of original(not patched)</TD>
		</TR>
</TABLE>
<!-- ************************************************************************** -->
<HR>
<A NAME="table3"><H1>Sheet 4: <EM>Step III</EM></H1></A>
<TABLE CELLSPACING="0" COLS="4" BORDER="0">
	<COLGROUP WIDTH="296"></COLGROUP>
	<COLGROUP WIDTH="86"></COLGROUP>
	<COLGROUP WIDTH="116"></COLGROUP>
	<COLGROUP WIDTH="85"></COLGROUP>
	<TR>
		<TD COLSPAN=6 HEIGHT="17" ALIGN="LEFT">Using Fpc, &ldquo;constref&rdquo; and &ldquo;var&rdquo; produce the same binary code.</TD>
		</TR>
	<TR>
		<TD COLSPAN=6 HEIGHT="17" ALIGN="LEFT">In order to remove a double influence of the same binary code, functions using &ldquo;constref&rdquo; have been removed.</TD>
		</TR>
	<TR>
		<TD HEIGHT="16" ALIGN="LEFT"><BR></TD>
		<TD ALIGN="LEFT"><BR></TD>
		<TD ALIGN="LEFT"><BR></TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT"><BR></TD>
		<TD ALIGN="CENTER">Original[ms]</TD>
		<TD ALIGN="CENTER">NOPInserted[ms]</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__equal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2567" SDNUM="1033;">2567</TD>
		<TD ALIGN="CENTER" SDVAL="2573" SDNUM="1033;">2573</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__equal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2794" SDNUM="1033;">2794</TD>
		<TD ALIGN="CENTER" SDVAL="2808" SDNUM="1033;">2808</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__notequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2699" SDNUM="1033;">2699</TD>
		<TD ALIGN="CENTER" SDVAL="3141" SDNUM="1033;">3141</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__notequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2481" SDNUM="1033;">2481</TD>
		<TD ALIGN="CENTER" SDVAL="3061" SDNUM="1033;">3061</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__less_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2820" SDNUM="1033;">2820</TD>
		<TD ALIGN="CENTER" SDVAL="2827" SDNUM="1033;">2827</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__less_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2549" SDNUM="1033;">2549</TD>
		<TD ALIGN="CENTER" SDVAL="2558" SDNUM="1033;">2558</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__lessorequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2309" SDNUM="1033;">2309</TD>
		<TD ALIGN="CENTER" SDVAL="2320" SDNUM="1033;">2320</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__lessorequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2293" SDNUM="1033;">2293</TD>
		<TD ALIGN="CENTER" SDVAL="2293" SDNUM="1033;">2293</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__more_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2819" SDNUM="1033;">2819</TD>
		<TD ALIGN="CENTER" SDVAL="2830" SDNUM="1033;">2830</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__more_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2796" SDNUM="1033;">2796</TD>
		<TD ALIGN="CENTER" SDVAL="2807" SDNUM="1033;">2807</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__moreorequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2313" SDNUM="1033;">2313</TD>
		<TD ALIGN="CENTER" SDVAL="2316" SDNUM="1033;">2316</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__moreorequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2540" SDNUM="1033;">2540</TD>
		<TD ALIGN="CENTER" SDVAL="2547" SDNUM="1033;">2547</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__iszero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2573" SDNUM="1033;">2573</TD>
		<TD ALIGN="CENTER" SDVAL="2571" SDNUM="1033;">2571</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__iszero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2825" SDNUM="1033;">2825</TD>
		<TD ALIGN="CENTER" SDVAL="2805" SDNUM="1033;">2805</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__isnotzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2540" SDNUM="1033;">2540</TD>
		<TD ALIGN="CENTER" SDVAL="2570" SDNUM="1033;">2570</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__isnotzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2303" SDNUM="1033;">2303</TD>
		<TD ALIGN="CENTER" SDVAL="2298" SDNUM="1033;">2298</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__lessthanzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2812" SDNUM="1033;">2812</TD>
		<TD ALIGN="CENTER" SDVAL="2828" SDNUM="1033;">2828</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__lessthanzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2570" SDNUM="1033;">2570</TD>
		<TD ALIGN="CENTER" SDVAL="2576" SDNUM="1033;">2576</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__lessorequaltozero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2291" SDNUM="1033;">2291</TD>
		<TD ALIGN="CENTER" SDVAL="5758" SDNUM="1033;">5758</TD>
		<TD ALIGN="LEFT">*</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__lessorequaltozero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2287" SDNUM="1033;">2287</TD>
		<TD ALIGN="CENTER" SDVAL="5762" SDNUM="1033;">5762</TD>
		<TD ALIGN="LEFT">*</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__morethanzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2828" SDNUM="1033;">2828</TD>
		<TD ALIGN="CENTER" SDVAL="2790" SDNUM="1033;">2790</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__morethanzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2822" SDNUM="1033;">2822</TD>
		<TD ALIGN="CENTER" SDVAL="2822" SDNUM="1033;">2822</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__moreorequaltozero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2285" SDNUM="1033;">2285</TD>
		<TD ALIGN="CENTER" SDVAL="2284" SDNUM="1033;">2284</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__moreorequaltozero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2574" SDNUM="1033;">2574</TD>
		<TD ALIGN="CENTER" SDVAL="2563" SDNUM="1033;">2563</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_equal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6123" SDNUM="1033;">6123</TD>
		<TD ALIGN="CENTER" SDVAL="2542" SDNUM="1033;">2542</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_equal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2795" SDNUM="1033;">2795</TD>
		<TD ALIGN="CENTER" SDVAL="2821" SDNUM="1033;">2821</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_notequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2821" SDNUM="1033;">2821</TD>
		<TD ALIGN="CENTER" SDVAL="2816" SDNUM="1033;">2816</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_notequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6127" SDNUM="1033;">6127</TD>
		<TD ALIGN="CENTER" SDVAL="2597" SDNUM="1033;">2597</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_less_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2820" SDNUM="1033;">2820</TD>
		<TD ALIGN="CENTER" SDVAL="2822" SDNUM="1033;">2822</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_less_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6159" SDNUM="1033;">6159</TD>
		<TD ALIGN="CENTER" SDVAL="2613" SDNUM="1033;">2613</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_lessorequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6126" SDNUM="1033;">6126</TD>
		<TD ALIGN="CENTER" SDVAL="2568" SDNUM="1033;">2568</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_lessorequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6127" SDNUM="1033;">6127</TD>
		<TD ALIGN="CENTER" SDVAL="2544" SDNUM="1033;">2544</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_more_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2825" SDNUM="1033;">2825</TD>
		<TD ALIGN="CENTER" SDVAL="2818" SDNUM="1033;">2818</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_more_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2819" SDNUM="1033;">2819</TD>
		<TD ALIGN="CENTER" SDVAL="2790" SDNUM="1033;">2790</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_moreorequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6121" SDNUM="1033;">6121</TD>
		<TD ALIGN="CENTER" SDVAL="2568" SDNUM="1033;">2568</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_moreorequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2792" SDNUM="1033;">2792</TD>
		<TD ALIGN="CENTER" SDVAL="2792" SDNUM="1033;">2792</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_iszero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6154" SDNUM="1033;">6154</TD>
		<TD ALIGN="CENTER" SDVAL="2566" SDNUM="1033;">2566</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_iszero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2793" SDNUM="1033;">2793</TD>
		<TD ALIGN="CENTER" SDVAL="2796" SDNUM="1033;">2796</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_isnotzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2820" SDNUM="1033;">2820</TD>
		<TD ALIGN="CENTER" SDVAL="2815" SDNUM="1033;">2815</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_isnotzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6144" SDNUM="1033;">6144</TD>
		<TD ALIGN="CENTER" SDVAL="2573" SDNUM="1033;">2573</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_lessthanzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2800" SDNUM="1033;">2800</TD>
		<TD ALIGN="CENTER" SDVAL="2793" SDNUM="1033;">2793</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_lessthanzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6175" SDNUM="1033;">6175</TD>
		<TD ALIGN="CENTER" SDVAL="2568" SDNUM="1033;">2568</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_lessorequaltozero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6182" SDNUM="1033;">6182</TD>
		<TD ALIGN="CENTER" SDVAL="2601" SDNUM="1033;">2601</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_lessorequaltozero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6186" SDNUM="1033;">6186</TD>
		<TD ALIGN="CENTER" SDVAL="2632" SDNUM="1033;">2632</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_morethanzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2879" SDNUM="1033;">2879</TD>
		<TD ALIGN="CENTER" SDVAL="2853" SDNUM="1033;">2853</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_morethanzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2846" SDNUM="1033;">2846</TD>
		<TD ALIGN="CENTER" SDVAL="2883" SDNUM="1033;">2883</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_moreorequaltozero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6201" SDNUM="1033;">6201</TD>
		<TD ALIGN="CENTER" SDVAL="2601" SDNUM="1033;">2601</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_moreorequaltozero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2846" SDNUM="1033;">2846</TD>
		<TD ALIGN="CENTER" SDVAL="2882" SDNUM="1033;">2882</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_equal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2628" SDNUM="1033;">2628</TD>
		<TD ALIGN="CENTER" SDVAL="2608" SDNUM="1033;">2608</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_equal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2846" SDNUM="1033;">2846</TD>
		<TD ALIGN="CENTER" SDVAL="2880" SDNUM="1033;">2880</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_notequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2625" SDNUM="1033;">2625</TD>
		<TD ALIGN="CENTER" SDVAL="2627" SDNUM="1033;">2627</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_notequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2345" SDNUM="1033;">2345</TD>
		<TD ALIGN="CENTER" SDVAL="2358" SDNUM="1033;">2358</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_less_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2875" SDNUM="1033;">2875</TD>
		<TD ALIGN="CENTER" SDVAL="2881" SDNUM="1033;">2881</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_less_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2601" SDNUM="1033;">2601</TD>
		<TD ALIGN="CENTER" SDVAL="2604" SDNUM="1033;">2604</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_lessorequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2373" SDNUM="1033;">2373</TD>
		<TD ALIGN="CENTER" SDVAL="2387" SDNUM="1033;">2387</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_lessorequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2346" SDNUM="1033;">2346</TD>
		<TD ALIGN="CENTER" SDVAL="2348" SDNUM="1033;">2348</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_more_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2871" SDNUM="1033;">2871</TD>
		<TD ALIGN="CENTER" SDVAL="2881" SDNUM="1033;">2881</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_more_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2856" SDNUM="1033;">2856</TD>
		<TD ALIGN="CENTER" SDVAL="2860" SDNUM="1033;">2860</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_moreorequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="3009" SDNUM="1033;">3009</TD>
		<TD ALIGN="CENTER" SDVAL="2998" SDNUM="1033;">2998</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_moreorequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="3027" SDNUM="1033;">3027</TD>
		<TD ALIGN="CENTER" SDVAL="3270" SDNUM="1033;">3270</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_iszero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2597" SDNUM="1033;">2597</TD>
		<TD ALIGN="CENTER" SDVAL="2630" SDNUM="1033;">2630</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_iszero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2875" SDNUM="1033;">2875</TD>
		<TD ALIGN="CENTER" SDVAL="2883" SDNUM="1033;">2883</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_isnotzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2602" SDNUM="1033;">2602</TD>
		<TD ALIGN="CENTER" SDVAL="2602" SDNUM="1033;">2602</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_isnotzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2372" SDNUM="1033;">2372</TD>
		<TD ALIGN="CENTER" SDVAL="2377" SDNUM="1033;">2377</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_lessthanzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2853" SDNUM="1033;">2853</TD>
		<TD ALIGN="CENTER" SDVAL="2857" SDNUM="1033;">2857</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_lessthanzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2629" SDNUM="1033;">2629</TD>
		<TD ALIGN="CENTER" SDVAL="2634" SDNUM="1033;">2634</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_lessorequaltozero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2345" SDNUM="1033;">2345</TD>
		<TD ALIGN="CENTER" SDVAL="2351" SDNUM="1033;">2351</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_lessorequaltozero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2367" SDNUM="1033;">2367</TD>
		<TD ALIGN="CENTER" SDVAL="2377" SDNUM="1033;">2377</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_morethanzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2851" SDNUM="1033;">2851</TD>
		<TD ALIGN="CENTER" SDVAL="2860" SDNUM="1033;">2860</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_morethanzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2886" SDNUM="1033;">2886</TD>
		<TD ALIGN="CENTER" SDVAL="2883" SDNUM="1033;">2883</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_moreorequaltozero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2343" SDNUM="1033;">2343</TD>
		<TD ALIGN="CENTER" SDVAL="2356" SDNUM="1033;">2356</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_const_moreorequaltozero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2625" SDNUM="1033;">2625</TD>
		<TD ALIGN="CENTER" SDVAL="2629" SDNUM="1033;">2629</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="16" ALIGN="LEFT">int64__equal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2601" SDNUM="1033;">2601</TD>
		<TD ALIGN="CENTER" SDVAL="2625" SDNUM="1033;">2625</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="16" ALIGN="LEFT">int64__equal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2375" SDNUM="1033;">2375</TD>
		<TD ALIGN="CENTER" SDVAL="2349" SDNUM="1033;">2349</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__notequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2600" SDNUM="1033;">2600</TD>
		<TD ALIGN="CENTER" SDVAL="2626" SDNUM="1033;">2626</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__notequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2885" SDNUM="1033;">2885</TD>
		<TD ALIGN="CENTER" SDVAL="2859" SDNUM="1033;">2859</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="16" ALIGN="LEFT">int64__less_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2345" SDNUM="1033;">2345</TD>
		<TD ALIGN="CENTER" SDVAL="2370" SDNUM="1033;">2370</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="16" ALIGN="LEFT">int64__less_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2628" SDNUM="1033;">2628</TD>
		<TD ALIGN="CENTER" SDVAL="2604" SDNUM="1033;">2604</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__lessorequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2856" SDNUM="1033;">2856</TD>
		<TD ALIGN="CENTER" SDVAL="2881" SDNUM="1033;">2881</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__lessorequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2878" SDNUM="1033;">2878</TD>
		<TD ALIGN="CENTER" SDVAL="2854" SDNUM="1033;">2854</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="16" ALIGN="LEFT">int64__more_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2545" SDNUM="1033;">2545</TD>
		<TD ALIGN="CENTER" SDVAL="2375" SDNUM="1033;">2375</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="16" ALIGN="LEFT">int64__more_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2418" SDNUM="1033;">2418</TD>
		<TD ALIGN="CENTER" SDVAL="2522" SDNUM="1033;">2522</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__moreorequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2897" SDNUM="1033;">2897</TD>
		<TD ALIGN="CENTER" SDVAL="2896" SDNUM="1033;">2896</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__moreorequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2606" SDNUM="1033;">2606</TD>
		<TD ALIGN="CENTER" SDVAL="2631" SDNUM="1033;">2631</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__iszero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2630" SDNUM="1033;">2630</TD>
		<TD ALIGN="CENTER" SDVAL="2603" SDNUM="1033;">2603</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__iszero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2346" SDNUM="1033;">2346</TD>
		<TD ALIGN="CENTER" SDVAL="2349" SDNUM="1033;">2349</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__isnotzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2625" SDNUM="1033;">2625</TD>
		<TD ALIGN="CENTER" SDVAL="2624" SDNUM="1033;">2624</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__isnotzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2858" SDNUM="1033;">2858</TD>
		<TD ALIGN="CENTER" SDVAL="2883" SDNUM="1033;">2883</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__lessthanzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2370" SDNUM="1033;">2370</TD>
		<TD ALIGN="CENTER" SDVAL="2347" SDNUM="1033;">2347</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__lessthanzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2598" SDNUM="1033;">2598</TD>
		<TD ALIGN="CENTER" SDVAL="2622" SDNUM="1033;">2622</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__lessorequaltozero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2879" SDNUM="1033;">2879</TD>
		<TD ALIGN="CENTER" SDVAL="2854" SDNUM="1033;">2854</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__lessorequaltozero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2851" SDNUM="1033;">2851</TD>
		<TD ALIGN="CENTER" SDVAL="2877" SDNUM="1033;">2877</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__morethanzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2371" SDNUM="1033;">2371</TD>
		<TD ALIGN="CENTER" SDVAL="2351" SDNUM="1033;">2351</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__morethanzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2349" SDNUM="1033;">2349</TD>
		<TD ALIGN="CENTER" SDVAL="2371" SDNUM="1033;">2371</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__moreorequaltozero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2878" SDNUM="1033;">2878</TD>
		<TD ALIGN="CENTER" SDVAL="2854" SDNUM="1033;">2854</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64__moreorequaltozero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2600" SDNUM="1033;">2600</TD>
		<TD ALIGN="CENTER" SDVAL="2625" SDNUM="1033;">2625</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="16" ALIGN="LEFT">int64_var_equal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6192" SDNUM="1033;">6192</TD>
		<TD ALIGN="CENTER" SDVAL="3114" SDNUM="1033;">3114</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="16" ALIGN="LEFT">int64_var_equal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2528" SDNUM="1033;">2528</TD>
		<TD ALIGN="CENTER" SDVAL="2888" SDNUM="1033;">2888</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_notequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2625" SDNUM="1033;">2625</TD>
		<TD ALIGN="CENTER" SDVAL="2877" SDNUM="1033;">2877</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_notequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6422" SDNUM="1033;">6422</TD>
		<TD ALIGN="CENTER" SDVAL="3105" SDNUM="1033;">3105</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="16" ALIGN="LEFT">int64_var_less_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2346" SDNUM="1033;">2346</TD>
		<TD ALIGN="CENTER" SDVAL="2622" SDNUM="1033;">2622</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="16" ALIGN="LEFT">int64_var_less_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6192" SDNUM="1033;">6192</TD>
		<TD ALIGN="CENTER" SDVAL="2852" SDNUM="1033;">2852</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_lessorequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6429" SDNUM="1033;">6429</TD>
		<TD ALIGN="CENTER" SDVAL="3132" SDNUM="1033;">3132</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_lessorequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6424" SDNUM="1033;">6424</TD>
		<TD ALIGN="CENTER" SDVAL="3129" SDNUM="1033;">3129</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="16" ALIGN="LEFT">int64_var_more_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2366" SDNUM="1033;">2366</TD>
		<TD ALIGN="CENTER" SDVAL="2597" SDNUM="1033;">2597</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="16" ALIGN="LEFT">int64_var_more_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2345" SDNUM="1033;">2345</TD>
		<TD ALIGN="CENTER" SDVAL="2625" SDNUM="1033;">2625</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_moreorequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6421" SDNUM="1033;">6421</TD>
		<TD ALIGN="CENTER" SDVAL="3105" SDNUM="1033;">3105</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_moreorequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2627" SDNUM="1033;">2627</TD>
		<TD ALIGN="CENTER" SDVAL="2883" SDNUM="1033;">2883</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_iszero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6169" SDNUM="1033;">6169</TD>
		<TD ALIGN="CENTER" SDVAL="2850" SDNUM="1033;">2850</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_iszero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2366" SDNUM="1033;">2366</TD>
		<TD ALIGN="CENTER" SDVAL="2620" SDNUM="1033;">2620</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_isnotzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2595" SDNUM="1033;">2595</TD>
		<TD ALIGN="CENTER" SDVAL="2854" SDNUM="1033;">2854</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_isnotzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6419" SDNUM="1033;">6419</TD>
		<TD ALIGN="CENTER" SDVAL="3125" SDNUM="1033;">3125</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_lessthanzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="5827" SDNUM="1033;">5827</TD>
		<TD ALIGN="CENTER" SDVAL="4066" SDNUM="1033;">4066</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_lessthanzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6167" SDNUM="1033;">6167</TD>
		<TD ALIGN="CENTER" SDVAL="5619" SDNUM="1033;">5619</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_lessorequaltozero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6422" SDNUM="1033;">6422</TD>
		<TD ALIGN="CENTER" SDVAL="3128" SDNUM="1033;">3128</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_lessorequaltozero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="6426" SDNUM="1033;">6426</TD>
		<TD ALIGN="CENTER" SDVAL="3100" SDNUM="1033;">3100</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_morethanzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2367" SDNUM="1033;">2367</TD>
		<TD ALIGN="CENTER" SDVAL="2623" SDNUM="1033;">2623</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_morethanzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2340" SDNUM="1033;">2340</TD>
		<TD ALIGN="CENTER" SDVAL="2593" SDNUM="1033;">2593</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_moreorequaltozero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="6444" SDNUM="1033;">6444</TD>
		<TD ALIGN="CENTER" SDVAL="3128" SDNUM="1033;">3128</TD>
		<TD ALIGN="LEFT">**</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_var_moreorequaltozero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2599" SDNUM="1033;">2599</TD>
		<TD ALIGN="CENTER" SDVAL="2850" SDNUM="1033;">2850</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_equal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2622" SDNUM="1033;">2622</TD>
		<TD ALIGN="CENTER" SDVAL="2622" SDNUM="1033;">2622</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_equal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2343" SDNUM="1033;">2343</TD>
		<TD ALIGN="CENTER" SDVAL="2339" SDNUM="1033;">2339</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_notequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2623" SDNUM="1033;">2623</TD>
		<TD ALIGN="CENTER" SDVAL="2629" SDNUM="1033;">2629</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_notequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2850" SDNUM="1033;">2850</TD>
		<TD ALIGN="CENTER" SDVAL="2871" SDNUM="1033;">2871</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_less_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2370" SDNUM="1033;">2370</TD>
		<TD ALIGN="CENTER" SDVAL="2343" SDNUM="1033;">2343</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_less_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2594" SDNUM="1033;">2594</TD>
		<TD ALIGN="CENTER" SDVAL="2626" SDNUM="1033;">2626</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_lessorequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2879" SDNUM="1033;">2879</TD>
		<TD ALIGN="CENTER" SDVAL="2849" SDNUM="1033;">2849</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_lessorequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2849" SDNUM="1033;">2849</TD>
		<TD ALIGN="CENTER" SDVAL="2873" SDNUM="1033;">2873</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_more_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2547" SDNUM="1033;">2547</TD>
		<TD ALIGN="CENTER" SDVAL="2520" SDNUM="1033;">2520</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_more_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2526" SDNUM="1033;">2526</TD>
		<TD ALIGN="CENTER" SDVAL="2554" SDNUM="1033;">2554</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_moreorequal_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2870" SDNUM="1033;">2870</TD>
		<TD ALIGN="CENTER" SDVAL="2847" SDNUM="1033;">2847</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_moreorequal_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2624" SDNUM="1033;">2624</TD>
		<TD ALIGN="CENTER" SDVAL="2628" SDNUM="1033;">2628</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_iszero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2600" SDNUM="1033;">2600</TD>
		<TD ALIGN="CENTER" SDVAL="2595" SDNUM="1033;">2595</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_iszero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2368" SDNUM="1033;">2368</TD>
		<TD ALIGN="CENTER" SDVAL="2370" SDNUM="1033;">2370</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_isnotzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2595" SDNUM="1033;">2595</TD>
		<TD ALIGN="CENTER" SDVAL="2599" SDNUM="1033;">2599</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_isnotzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2879" SDNUM="1033;">2879</TD>
		<TD ALIGN="CENTER" SDVAL="2878" SDNUM="1033;">2878</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_lessthanzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2340" SDNUM="1033;">2340</TD>
		<TD ALIGN="CENTER" SDVAL="2342" SDNUM="1033;">2342</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_lessthanzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2619" SDNUM="1033;">2619</TD>
		<TD ALIGN="CENTER" SDVAL="2620" SDNUM="1033;">2620</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_lessorequaltozero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2860" SDNUM="1033;">2860</TD>
		<TD ALIGN="CENTER" SDVAL="2852" SDNUM="1033;">2852</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_lessorequaltozero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2874" SDNUM="1033;">2874</TD>
		<TD ALIGN="CENTER" SDVAL="2875" SDNUM="1033;">2875</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_morethanzero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2345" SDNUM="1033;">2345</TD>
		<TD ALIGN="CENTER" SDVAL="2370" SDNUM="1033;">2370</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_morethanzero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2366" SDNUM="1033;">2366</TD>
		<TD ALIGN="CENTER" SDVAL="2346" SDNUM="1033;">2346</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_moreorequaltozero_(0,0):</TD>
		<TD ALIGN="CENTER" SDVAL="2853" SDNUM="1033;">2853</TD>
		<TD ALIGN="CENTER" SDVAL="2875" SDNUM="1033;">2875</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">int64_const_moreorequaltozero_(0,1):</TD>
		<TD ALIGN="CENTER" SDVAL="2640" SDNUM="1033;">2640</TD>
		<TD ALIGN="CENTER" SDVAL="2595" SDNUM="1033;">2595</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="16" ALIGN="LEFT">Elapsed time:</TD>
		<TD ALIGN="CENTER" SDVAL="468201" SDNUM="1033;">468201</TD>
		<TD ALIGN="CENTER" SDVAL="398158" SDNUM="1033;">398158</TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="16" ALIGN="LEFT"><BR></TD>
		<TD ALIGN="LEFT"><BR></TD>
		<TD ALIGN="LEFT"><BR></TD>
		<TD ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD COLSPAN=4 HEIGHT="17" ALIGN="LEFT">&ldquo;Nop&rdquo; inserted takes ~85% the time needed of original(not patched)</TD>
		</TR>
</TABLE>
<!-- ************************************************************************** -->
<HR>
<A NAME="table4"><H1>Sheet 5: <EM>Observations</EM></H1></A>
<TABLE CELLSPACING="0" COLS="1" BORDER="0">
	<COLGROUP WIDTH="735"></COLGROUP>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">A significant improvement of code execution speed has been observed following the &ldquo;nop&rdquo; insertions.</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">While the pair of &ldquo;nop&rdquo;s removed many anomalies, it also added one(at longint__lessorequaltozero).</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">However, as average, the number of anomalies removed greatly exceeded the slowdowns added.</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">Not only that the anomalies appear to be connected to the conditional jump type, but also a partial pattern appeared.</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">If an anomaly appears, it's likely to appear in two places, connected by negating the condition and switching code order.</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">Examples:</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_equal_(0,0): 6123 ms</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_equal_(0,1): 2795 ms</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_notequal_(0,0): 2821 ms</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_notequal_(0,1): 6127 ms</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">or</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_lessorequal_(0,0): 6126 ms</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_lessorequal_(0,1): 6127 ms</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_more_(0,0): 2825 ms</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_more_(0,1): 2819 ms</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">or</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_lessthanzero_(0,0): 2800 ms</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_lessthanzero_(0,1): 6175 ms</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_moreorequaltozero_(0,0): 6201 ms</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_moreorequaltozero_(0,1): 2846 ms</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">and so on.</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT"><BR></TD>
	</TR>
	<TR>
		<TD HEIGHT="16" ALIGN="LEFT">Anomalies may appear no matter the conditional branch followed.</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">Examples:</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__lessorequaltozero_(0,0): 5758 ms</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint__lessorequaltozero_(0,1): 5762 ms</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">or</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_lessorequal_(0,0): 6126 ms</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_lessorequal_(0,1): 6127 ms</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">or</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_lessorequaltozero_(0,0): 6182 ms</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">longint_var_lessorequaltozero_(0,1): 6186 ms</TD>
	</TR>
	<TR>
		<TD HEIGHT="17" ALIGN="LEFT">and so on.</TD>
	</TR>
</TABLE>
<!-- ************************************************************************** -->
</BODY>

</HTML>
Detailed_analysis.html (170,931 bytes)   

lagprogramming

2014-10-16 12:59

reporter   ~0078273

1)
[fpc-devel] Registers allocation technique
http://lists.freepascal.org/pipermail/fpc-devel/2014-October/034523.html

presents a situation where simplifying a function by removing a local variable lead to a 10% speed decrease("PosWISHTORUNFASTEST" vs. "PosFASTER").
Inserting the pair of nops lead to changing the results "PosWISHTORUNFASTEST" running now faster than "PosFASTER"(as it should run).

2)
An attachment(Detailed_analysis.html) has been added where most conditional jump types were measured.

Do-wan Kim

2014-10-17 00:49

reporter   ~0078295

It will better current code generations except few worst cases.

Florian

2014-12-07 17:27

administrator   ~0079690

Without a detailed description why inserting nops help a certain processor, I see no reason to apply one of the patches.

lagprogramming

2014-12-07 21:57

reporter   ~0079692

I don't see a reason for main developers to close the report either. The problem persists.
   If you want to close the ticket without solving the problem and without being bothered by other users in the future, why don't you close the report with "won't fix" as a resolution!?
   If you(or somebody else) want to solve the problem(something that you could just have asked instead of closing the report without notice), here you'll find some tips.
   The nop insertions are a workaround that I've worked hard to find. Recently I've discovered that apparently AMD recommended an even better workaround: the first nop is useless while the last one can be replaced with a prefix.
But that solves only half the problem. Apparently, AMD K8 series CPUs conditional jumps are affected by alignment. Also, the number of consecutive conditional jumps might be a problem.

Details:
http://board.flatassembler.net/topic.php?t=11196&view=previous
http://www.agner.org/optimize/microarchitecture.pdf#page=30&zoom=auto,0,380

Florian

2014-12-07 22:10

administrator   ~0079693

The information here is simply useless since it contains a lot of noise, this is why I closed it. If you want it fixed, make a new report with clear information what is wrong and why, which processors are affected, which not etc.

Issue History

Date Modified Username Field Change
2014-04-28 18:04 lagprogramming New Issue
2014-04-28 18:04 lagprogramming File Added: inefficientcode.zip
2014-04-28 22:59 Jonas Maebe Note Added: 0074648
2014-04-28 22:59 Jonas Maebe Note Edited: 0074648 View Revisions
2014-04-28 23:11 Jonas Maebe Note Added: 0074649
2014-04-29 15:45 Thaddy de Koning Note Added: 0074660
2014-04-29 15:47 Thaddy de Koning Note Edited: 0074660 View Revisions
2014-04-29 15:48 Thaddy de Koning Note Edited: 0074660 View Revisions
2014-04-29 15:56 Jonas Maebe Note Added: 0074661
2014-04-29 16:10 Jonas Maebe Severity minor => feature
2014-04-29 17:53 lagprogramming Note Added: 0074667
2014-04-29 18:19 Jonas Maebe Note Added: 0074669
2014-04-29 20:27 Florian Note Added: 0074674
2014-04-29 20:28 Florian Note Edited: 0074674 View Revisions
2014-04-29 20:28 Florian Note Edited: 0074674 View Revisions
2014-04-29 20:31 Florian Note Edited: 0074674 View Revisions
2014-09-10 15:45 lagprogramming Note Added: 0077052
2014-09-10 16:14 lagprogramming Note Edited: 0077052 View Revisions
2014-09-10 20:06 lagprogramming Note Added: 0077067
2014-09-10 20:08 lagprogramming Note Edited: 0077067 View Revisions
2014-09-11 03:20 Do-wan Kim Note Added: 0077076
2014-09-11 12:13 lagprogramming Note Edited: 0077067 View Revisions
2014-09-11 14:35 lagprogramming Note Added: 0077083
2014-09-13 18:45 lagprogramming File Added: AMDSempronMobile3500pluswine
2014-09-13 18:45 lagprogramming File Added: AMDSempronMobile3500plusx8664.txt
2014-09-13 18:46 lagprogramming File Added: ifthenelse.zip
2014-09-13 19:16 lagprogramming File Added: IntelAtomCPUN2701.60GHzi386.txt
2014-09-14 23:22 Do-wan Kim Note Added: 0077247
2014-09-26 10:51 lagprogramming Note Added: 0077680
2014-09-26 10:52 lagprogramming Note Edited: 0077680 View Revisions
2014-09-26 11:24 Jonas Maebe Note Added: 0077681
2014-09-26 18:58 lagprogramming Note Added: 0077705
2014-09-26 19:26 Sergei Gorelkin Note Added: 0077707
2014-09-27 11:46 EgonHugeist/ZeosDevTeam Note Added: 0077724
2014-09-27 12:17 Florian Note Added: 0077725
2014-09-27 12:56 EgonHugeist/ZeosDevTeam Note Added: 0077729
2014-09-27 13:11 EgonHugeist/ZeosDevTeam Note Edited: 0077729 View Revisions
2014-09-27 13:11 EgonHugeist/ZeosDevTeam Note Edited: 0077729 View Revisions
2014-10-03 13:50 lagprogramming File Added: AMDMobileSempronSingleSeriesTimingsWithDifferentCPUFrequencies.txt
2014-10-03 13:52 lagprogramming File Added: AMDMobileSempronAssemblerCodeInfo.txt
2014-10-03 13:52 lagprogramming Note Added: 0077961
2014-10-03 14:29 lagprogramming Note Edited: 0077961 View Revisions
2014-10-05 00:23 Do-wan Kim Note Added: 0077992
2014-10-09 16:45 lagprogramming File Added: AMDMobileSempronNOPInstructionResults.txt
2014-10-09 16:46 lagprogramming Note Added: 0078109
2014-10-10 05:26 Do-wan Kim File Added: nop_insert_cgx86.pas.patch
2014-10-10 05:27 Do-wan Kim Note Added: 0078126
2014-10-10 16:20 lagprogramming File Added: svntimings.txt
2014-10-10 16:22 lagprogramming Note Added: 0078138
2014-10-11 00:56 Do-wan Kim File Added: proc_entry_exit_nop.patch
2014-10-11 01:08 Do-wan Kim Note Added: 0078152
2014-10-11 02:13 Do-wan Kim File Added: proc_entry_exit_nop_1.patch
2014-10-11 02:15 Do-wan Kim Note Edited: 0078152 View Revisions
2014-10-11 04:40 Do-wan Kim File Added: proc_entry_exit_nop_32.patch
2014-10-11 04:47 Do-wan Kim Note Edited: 0078152 View Revisions
2014-10-11 04:49 Do-wan Kim Note Edited: 0078152 View Revisions
2014-10-12 01:46 Do-wan Kim File Added: proc_entry_exit_nop_3264_fix.patch
2014-10-12 01:49 Do-wan Kim Note Edited: 0078152 View Revisions
2014-10-12 03:19 Do-wan Kim File Added: proc_entry_exit_nop_3264_fix_1.patch
2014-10-12 03:20 Do-wan Kim Note Edited: 0078152 View Revisions
2014-10-12 21:20 lagprogramming Note Added: 0078176
2014-10-13 02:58 Do-wan Kim Note Added: 0078187
2014-10-13 03:17 Do-wan Kim File Added: proc_entry_exit_nop_3264_nostackframe.patch
2014-10-13 03:21 Do-wan Kim Note Edited: 0078187 View Revisions
2014-10-13 03:26 Jeppe Johansen Note Added: 0078188
2014-10-13 21:43 lagprogramming Note Added: 0078205
2014-10-13 21:45 lagprogramming Note Added: 0078206
2014-10-14 02:04 Do-wan Kim Note Added: 0078212
2014-10-16 12:58 lagprogramming File Added: Detailed_analysis.html
2014-10-16 12:59 lagprogramming Note Added: 0078273
2014-10-17 00:49 Do-wan Kim Note Added: 0078295
2014-12-07 17:27 Florian Note Added: 0079690
2014-12-07 17:27 Florian Status new => resolved
2014-12-07 17:27 Florian Resolution open => no change required
2014-12-07 17:27 Florian Assigned To => Florian
2014-12-07 21:57 lagprogramming Note Added: 0079692
2014-12-07 21:57 lagprogramming Status resolved => feedback
2014-12-07 21:57 lagprogramming Resolution no change required => reopened
2014-12-07 22:10 Florian Note Added: 0079693
2014-12-07 22:10 Florian Status feedback => resolved
2014-12-07 22:10 Florian Resolution reopened => no change required