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IDProjectCategoryView StatusLast Update
0033170FPCCompilerpublic2019-09-17 11:33
ReporterTimm ThalerAssigned ToFlorian 
PrioritynormalSeverityminorReproducibilityalways
Status resolvedResolutionfixed 
PlatformEmbeddedOSAVROS VersionAVR5
Product Version3.1.1Product BuildFPC 3.1.1-r38235 [2018/02/13] fo 
Target VersionFixed in Version3.1.1 
Summary0033170: AVR: CLR in ISR corrupts SREG
DescriptionAfter fixing the R1 bug in the ISR ( https://bugs.freepascal.org/view.php?id=33165) entering the ISR will clr R1 bevor saving the SREG. As clr changes the SREG the SREG is corrupted and the program may fail.

    push r1
    push r0
    clr r1
    in r0,63
    push r0

should be

    push r1
    push r0
    in r0,63
    push r0
    clr r1
TagsAVR
Fixed in Revision38241
FPCOldBugId
FPCTarget
Attached Files
  • cgcpu.patch (750 bytes)
    Index: compiler/avr/cgcpu.pas
    ===================================================================
    --- compiler/avr/cgcpu.pas	(revision 38233)
    +++ compiler/avr/cgcpu.pas	(working copy)
    @@ -1909,12 +1909,12 @@
                   if reg in regs then
                     list.concat(taicpu.op_reg(A_PUSH,newreg(R_INTREGISTER,reg,R_SUBWHOLE)));
     
    -            list.concat(taicpu.op_reg(A_CLR,NR_R1));
    -
                 { Save SREG }
                 list.concat(taicpu.op_reg_const(A_IN, NR_R0, $3F));
                 list.concat(taicpu.op_reg(A_PUSH, NR_R0));
     
    +            list.concat(taicpu.op_reg(A_CLR,NR_R1));
    +
                 if current_procinfo.framepointer<>NR_NO then
                   begin
                     list.concat(taicpu.op_reg_const(A_IN,NR_R28,NIO_SP_LO));
    
    cgcpu.patch (750 bytes)

Activities

Christo Crause

2018-02-14 18:25

reporter  

cgcpu.patch (750 bytes)
Index: compiler/avr/cgcpu.pas
===================================================================
--- compiler/avr/cgcpu.pas	(revision 38233)
+++ compiler/avr/cgcpu.pas	(working copy)
@@ -1909,12 +1909,12 @@
               if reg in regs then
                 list.concat(taicpu.op_reg(A_PUSH,newreg(R_INTREGISTER,reg,R_SUBWHOLE)));
 
-            list.concat(taicpu.op_reg(A_CLR,NR_R1));
-
             { Save SREG }
             list.concat(taicpu.op_reg_const(A_IN, NR_R0, $3F));
             list.concat(taicpu.op_reg(A_PUSH, NR_R0));
 
+            list.concat(taicpu.op_reg(A_CLR,NR_R1));
+
             if current_procinfo.framepointer<>NR_NO then
               begin
                 list.concat(taicpu.op_reg_const(A_IN,NR_R28,NIO_SP_LO));
cgcpu.patch (750 bytes)

Christo Crause

2018-02-14 18:29

reporter   ~0106390

I agree that CLR sets SVNZ bits of SREG. The fix appears to be simple, see attached patch.

Issue History

Date Modified Username Field Change
2018-02-14 15:33 Timm Thaler New Issue
2018-02-14 18:25 Christo Crause File Added: cgcpu.patch
2018-02-14 18:29 Christo Crause Note Added: 0106390
2018-02-14 20:28 Florian Fixed in Revision => 38241
2018-02-14 20:28 Florian Status new => resolved
2018-02-14 20:28 Florian Fixed in Version => 3.1.1
2018-02-14 20:28 Florian Resolution open => fixed
2018-02-14 20:28 Florian Assigned To => Florian
2019-09-17 11:33 Dimitrios Chr. Ioannidis Tag Attached: AVR