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IDProjectCategoryView StatusLast Update
0036686FPCCompilerpublic2020-02-09 14:14
ReporterChristo Crause Assigned ToFlorian  
PrioritynormalSeverityminorReproducibilityN/A
Status closedResolutionfixed 
Product Version3.3.1 
Fixed in Version3.3.1 
Summary0036686: AVR [patch] More avr1 controllers and remove attiny28 from avr25 makefile list.
DescriptionThis patch add the remaining, currently supported (described in device pack) avr1 controllers to FPC. Also removed attiny28 from avr25 makefile list.
TagsNo tags attached.
Fixed in Revision44136
FPCOldBugId
FPCTarget-
Attached Files

Activities

Christo Crause

2020-02-09 11:06

reporter  

avr1-controllers.patch (18,335 bytes)   
diff --git a/compiler/avr/cpuinfo.pas b/compiler/avr/cpuinfo.pas
index a1ddfbfc16..fad8c4bf73 100644
--- a/compiler/avr/cpuinfo.pas
+++ b/compiler/avr/cpuinfo.pas
@@ -200,8 +200,11 @@ Type
       ct_attiny5,
       ct_attiny9,
       ct_attiny10,
+      ct_attiny11,
+      ct_attiny12,
       ct_attiny13,
       ct_attiny13a,
+      ct_attiny15,
       ct_attiny20,
       ct_attiny24,
       ct_attiny24a,
@@ -496,8 +499,11 @@ Const
         ,(controllertypestr:'ATTINY5';controllerunitstr:'ATTINY5';cputype:cpu_avrtiny;fputype:fpu_soft;flashbase:0;flashsize:512;srambase:64;sramsize:32;eeprombase:0;eepromsize:0)
         ,(controllertypestr:'ATTINY9';controllerunitstr:'ATTINY9';cputype:cpu_avrtiny;fputype:fpu_soft;flashbase:0;flashsize:1024;srambase:64;sramsize:32;eeprombase:0;eepromsize:0)
         ,(controllertypestr:'ATTINY10';controllerunitstr:'ATTINY10';cputype:cpu_avrtiny;fputype:fpu_soft;flashbase:0;flashsize:1024;srambase:64;sramsize:32;eeprombase:0;eepromsize:0)
+        ,(controllertypestr:'ATTINY11';controllerunitstr:'ATTINY11';cputype:cpu_avr1;fputype:fpu_soft;flashbase:0;flashsize:1024;srambase:0;sramsize:0;eeprombase:0;eepromsize:0)
+        ,(controllertypestr:'ATTINY12';controllerunitstr:'ATTINY12';cputype:cpu_avr1;fputype:fpu_soft;flashbase:0;flashsize:1024;srambase:0;sramsize:0;eeprombase:0;eepromsize:64)
         ,(controllertypestr:'ATTINY13';controllerunitstr:'ATTINY13';cputype:cpu_avr25;fputype:fpu_soft;flashbase:0;flashsize:1024;srambase:96;sramsize:64;eeprombase:0;eepromsize:64)
         ,(controllertypestr:'ATTINY13A';controllerunitstr:'ATTINY13A';cputype:cpu_avr25;fputype:fpu_soft;flashbase:0;flashsize:1024;srambase:96;sramsize:64;eeprombase:0;eepromsize:64)
+        ,(controllertypestr:'ATTINY15';controllerunitstr:'ATTINY15';cputype:cpu_avr1;fputype:fpu_soft;flashbase:0;flashsize:1024;srambase:0;sramsize:0;eeprombase:0;eepromsize:64)
         ,(controllertypestr:'ATTINY20';controllerunitstr:'ATTINY20';cputype:cpu_avrtiny;fputype:fpu_soft;flashbase:0;flashsize:2048;srambase:64;sramsize:128;eeprombase:0;eepromsize:0)
         ,(controllertypestr:'ATTINY24';controllerunitstr:'ATTINY24';cputype:cpu_avr25;fputype:fpu_soft;flashbase:0;flashsize:2048;srambase:96;sramsize:128;eeprombase:0;eepromsize:128)
         ,(controllertypestr:'ATTINY24A';controllerunitstr:'ATTINY24A';cputype:cpu_avr25;fputype:fpu_soft;flashbase:0;flashsize:2048;srambase:96;sramsize:128;eeprombase:0;eepromsize:128)
diff --git a/rtl/embedded/Makefile b/rtl/embedded/Makefile
index df6c2388e6..3647327daf 100644
--- a/rtl/embedded/Makefile
+++ b/rtl/embedded/Makefile
@@ -390,7 +390,7 @@ CPU_UNITS=attiny4 attiny5 attiny9 attiny10 attiny20 attiny40 attiny102 attiny104
 CPU_UNITS_DEFINED=1
 endif
 ifeq ($(SUBARCH),avr1)
-CPU_UNITS=attiny28
+CPU_UNITS=attiny11 attiny12 attiny15 attiny28
 CPU_UNITS_DEFINED=1
 endif
 ifeq ($(SUBARCH),avr2)
@@ -398,7 +398,7 @@ CPU_UNITS=attiny26
 CPU_UNITS_DEFINED=1
 endif
 ifeq ($(SUBARCH),avr25)
-CPU_UNITS=attiny13 attiny13a attiny24 attiny24a attiny25 attiny28 attiny43u \
+CPU_UNITS=attiny13 attiny13a attiny24 attiny24a attiny25 attiny43u \
 	  attiny44 attiny44a attiny45 attiny48 attiny84a attiny84 attiny85 \
 	  attiny87 attiny88 attiny261 attiny261a attiny441 attiny461 attiny461a attiny828 \
 	  attiny841 attiny861 attiny861a attiny2313 attiny2313a attiny4313
diff --git a/rtl/embedded/Makefile.fpc b/rtl/embedded/Makefile.fpc
index 90260fb1ce..049ea7722d 100644
--- a/rtl/embedded/Makefile.fpc
+++ b/rtl/embedded/Makefile.fpc
@@ -106,7 +106,7 @@ CPU_UNITS=attiny4 attiny5 attiny9 attiny10 attiny20 attiny40 attiny102 attiny104
 CPU_UNITS_DEFINED=1
 endif
 ifeq ($(SUBARCH),avr1)
-CPU_UNITS=attiny28
+CPU_UNITS=attiny11 attiny12 attiny15 attiny28
 CPU_UNITS_DEFINED=1
 endif
 ifeq ($(SUBARCH),avr2)
@@ -114,7 +114,7 @@ CPU_UNITS=attiny26
 CPU_UNITS_DEFINED=1
 endif
 ifeq ($(SUBARCH),avr25)
-CPU_UNITS=attiny13 attiny13a attiny24 attiny24a attiny25 attiny28 attiny43u \
+CPU_UNITS=attiny13 attiny13a attiny24 attiny24a attiny25 attiny43u \
           attiny44 attiny44a attiny45 attiny48 attiny84a attiny84 attiny85 \
           attiny87 attiny88 attiny261 attiny261a attiny441 attiny461 attiny461a attiny828 \
           attiny841 attiny861 attiny861a attiny2313 attiny2313a attiny4313
diff --git a/rtl/embedded/avr/attiny11.pp b/rtl/embedded/avr/attiny11.pp
new file mode 100644
index 0000000000..acbeb050d7
--- /dev/null
+++ b/rtl/embedded/avr/attiny11.pp
@@ -0,0 +1,110 @@
+unit ATtiny11;
+
+{$goto on}
+interface
+
+var
+  ACSR: byte absolute $08;  // Analog Comparator Control And Status Register
+  PINB: byte absolute $16;  // Input Pins, Port B
+  DDRB: byte absolute $17;  // Data Direction Register, Port B
+  PORTB: byte absolute $18;  // Data Register, Port B
+  WDTCR: byte absolute $21;  // Watchdog Timer Control Register
+  TCNT0: byte absolute $32;  // Timer Counter 0
+  TCCR0: byte absolute $33;  // Timer/Counter0 Control Register
+  MCUSR: byte absolute $34;  // MCU Status register
+  MCUCR: byte absolute $35;  // MCU Control Register
+  TIFR: byte absolute $38;  // Timer/Counter Interrupt Flag register
+  TIMSK: byte absolute $39;  // Timer/Counter Interrupt Mask Register
+  GIFR: byte absolute $3A;  // General Interrupt Flag register
+  GIMSK: byte absolute $3B;  // General Interrupt Mask Register
+  SREG: byte absolute $3F;  // Status Register
+
+const
+  // Analog Comparator Control And Status Register
+  ACIS0 = $00;  // Analog Comparator Interrupt Mode Select bits
+  ACIS1 = $01;  // Analog Comparator Interrupt Mode Select bits
+  ACIE = $03;  
+  ACI = $04;  
+  ACO = $05;  
+  ACD = $07;  
+  // Data Register, Port B
+  PB0 = $00;  
+  PB1 = $01;  
+  PB2 = $02;  
+  PB3 = $03;  
+  PB4 = $04;  
+  // Watchdog Timer Control Register
+  WDP0 = $00;  // Watch Dog Timer Prescaler bits
+  WDP1 = $01;  // Watch Dog Timer Prescaler bits
+  WDP2 = $02;  // Watch Dog Timer Prescaler bits
+  WDE = $03;  
+  WDTOE = $04;  
+  // Timer/Counter0 Control Register
+  CS00 = $00;  
+  CS01 = $01;  
+  CS02 = $02;  
+  // MCU Status register
+  PORF = $00;  
+  EXTRF = $01;  
+  // MCU Control Register
+  ISC00 = $00;  // Interrupt Sense Control 0 bits
+  ISC01 = $01;  // Interrupt Sense Control 0 bits
+  SM = $04;  
+  SE = $05;  
+  // Timer/Counter Interrupt Flag register
+  TOV0 = $01;  
+  // Timer/Counter Interrupt Mask Register
+  TOIE0 = $01;  
+  // General Interrupt Flag register
+  PCIF = $05;  
+  INTF0 = $06;  
+  // General Interrupt Mask Register
+  PCIE = $05;  
+  INT0 = $06;  
+  // Status Register
+  C = $00;  
+  Z = $01;  
+  N = $02;  
+  V = $03;  
+  S = $04;  
+  H = $05;  
+  T = $06;  
+  I = $07;  
+
+
+implementation
+{$define RELBRANCHES}
+{$i avrcommon.inc}
+
+procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 1 External Interrupt 0
+procedure IO_PINS_ISR; external name 'IO_PINS_ISR'; // Interrupt 2 External Interrupt Request 0
+procedure TIMER0_OVF_ISR; external name 'TIMER0_OVF_ISR'; // Interrupt 3 Timer/Counter0 Overflow
+procedure ANA_COMP_ISR; external name 'ANA_COMP_ISR'; // Interrupt 4 Analog Comparator
+
+procedure _FPC_start; assembler; nostackframe;
+label
+  _start;
+asm
+  .init
+  .globl _start
+
+  rjmp _start
+  rjmp INT0_ISR
+  rjmp IO_PINS_ISR
+  rjmp TIMER0_OVF_ISR
+  rjmp ANA_COMP_ISR
+
+  {$i start_noram.inc}
+
+  .weak INT0_ISR
+  .weak IO_PINS_ISR
+  .weak TIMER0_OVF_ISR
+  .weak ANA_COMP_ISR
+
+  .set INT0_ISR, Default_IRQ_handler
+  .set IO_PINS_ISR, Default_IRQ_handler
+  .set TIMER0_OVF_ISR, Default_IRQ_handler
+  .set ANA_COMP_ISR, Default_IRQ_handler
+end;
+
+end.
diff --git a/rtl/embedded/avr/attiny12.pp b/rtl/embedded/avr/attiny12.pp
new file mode 100644
index 0000000000..667295d9c9
--- /dev/null
+++ b/rtl/embedded/avr/attiny12.pp
@@ -0,0 +1,136 @@
+unit ATtiny12;
+
+{$goto on}
+interface
+
+var
+  ACSR: byte absolute $08;  // Analog Comparator Control And Status Register
+  PINB: byte absolute $16;  // Input Pins, Port B
+  DDRB: byte absolute $17;  // Data Direction Register, Port B
+  PORTB: byte absolute $18;  // Data Register, Port B
+  EECR: byte absolute $1C;  // EEPROM Control Register
+  EEDR: byte absolute $1D;  // EEPROM Data Register
+  EEAR: byte absolute $1E;  // EEPROM Read/Write Access
+  WDTCR: byte absolute $21;  // Watchdog Timer Control Register
+  OSCCAL: byte absolute $31;  // Status Register
+  TCNT0: byte absolute $32;  // Timer Counter 0
+  TCCR0: byte absolute $33;  // Timer/Counter0 Control Register
+  MCUSR: byte absolute $34;  // MCU Status register
+  MCUCR: byte absolute $35;  // MCU Control Register
+  TIFR: byte absolute $38;  // Timer/Counter Interrupt Flag register
+  TIMSK: byte absolute $39;  // Timer/Counter Interrupt Mask Register
+  GIFR: byte absolute $3A;  // General Interrupt Flag register
+  GIMSK: byte absolute $3B;  // General Interrupt Mask Register
+  SREG: byte absolute $3F;  // Status Register
+
+const
+  // Analog Comparator Control And Status Register
+  ACIS0 = $00;  // Analog Comparator Interrupt Mode Select bits
+  ACIS1 = $01;  // Analog Comparator Interrupt Mode Select bits
+  ACIE = $03;  
+  ACI = $04;  
+  ACO = $05;  
+  AINBG = $06;  
+  ACD = $07;  
+  // Data Register, Port B
+  PB0 = $00;  
+  PB1 = $01;  
+  PB2 = $02;  
+  PB3 = $03;  
+  PB4 = $04;  
+  // EEPROM Control Register
+  EERE = $00;  
+  EEWE = $01;  
+  EEMWE = $02;  
+  EERIE = $03;  
+  // Watchdog Timer Control Register
+  WDP0 = $00;  // Watch Dog Timer Prescaler bits
+  WDP1 = $01;  // Watch Dog Timer Prescaler bits
+  WDP2 = $02;  // Watch Dog Timer Prescaler bits
+  WDE = $03;  
+  WDTOE = $04;  
+  // Status Register
+  OSCCAL0 = $00;  // Oscillator Calibration 
+  OSCCAL1 = $01;  // Oscillator Calibration 
+  OSCCAL2 = $02;  // Oscillator Calibration 
+  OSCCAL3 = $03;  // Oscillator Calibration 
+  OSCCAL4 = $04;  // Oscillator Calibration 
+  OSCCAL5 = $05;  // Oscillator Calibration 
+  OSCCAL6 = $06;  // Oscillator Calibration 
+  OSCCAL7 = $07;  // Oscillator Calibration 
+  // Timer/Counter0 Control Register
+  CS00 = $00;  
+  CS01 = $01;  
+  CS02 = $02;  
+  // MCU Status register
+  PORF = $00;  
+  EXTRF = $01;  
+  BORF = $02;  
+  WDRF = $03;  
+  // MCU Control Register
+  ISC00 = $00;  // Interrupt Sense Control 0 bits
+  ISC01 = $01;  // Interrupt Sense Control 0 bits
+  SM = $04;  
+  SE = $05;  
+  PUD = $06;  
+  // Timer/Counter Interrupt Flag register
+  TOV0 = $01;  
+  // Timer/Counter Interrupt Mask Register
+  TOIE0 = $01;  
+  // General Interrupt Flag register
+  PCIF = $05;  
+  INTF0 = $06;  
+  // General Interrupt Mask Register
+  PCIE = $05;  
+  INT0 = $06;  
+  // Status Register
+  C = $00;  
+  Z = $01;  
+  N = $02;  
+  V = $03;  
+  S = $04;  
+  H = $05;  
+  T = $06;  
+  I = $07;  
+
+
+implementation
+{$define RELBRANCHES}
+{$i avrcommon.inc}
+
+procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 1 External Interrupt 0
+procedure IO_PINS_ISR; external name 'IO_PINS_ISR'; // Interrupt 2 External Interrupt Request 0
+procedure TIMER0_OVF_ISR; external name 'TIMER0_OVF_ISR'; // Interrupt 3 Timer/Counter0 Overflow
+procedure EE_RDY_ISR; external name 'EE_RDY_ISR'; // Interrupt 4 EEPROM Ready
+procedure ANA_COMP_ISR; external name 'ANA_COMP_ISR'; // Interrupt 5 Analog Comparator
+
+procedure _FPC_start; assembler; nostackframe;
+label
+  _start;
+asm
+  .init
+  .globl _start
+
+  rjmp _start
+  rjmp INT0_ISR
+  rjmp IO_PINS_ISR
+  rjmp TIMER0_OVF_ISR
+  rjmp EE_RDY_ISR
+  rjmp ANA_COMP_ISR
+
+  {$i start_noram.inc}
+
+  .weak INT0_ISR
+  .weak IO_PINS_ISR
+  .weak TIMER0_OVF_ISR
+  .weak EE_RDY_ISR
+  .weak ANA_COMP_ISR
+
+  .set INT0_ISR, Default_IRQ_handler
+  .set IO_PINS_ISR, Default_IRQ_handler
+  .set TIMER0_OVF_ISR, Default_IRQ_handler
+  .set EE_RDY_ISR, Default_IRQ_handler
+  .set ANA_COMP_ISR, Default_IRQ_handler
+end;
+
+end.
diff --git a/rtl/embedded/avr/attiny15.pp b/rtl/embedded/avr/attiny15.pp
new file mode 100644
index 0000000000..1242a8de88
--- /dev/null
+++ b/rtl/embedded/avr/attiny15.pp
@@ -0,0 +1,192 @@
+unit ATtiny15;
+
+{$goto on}
+interface
+
+var
+  ADC: word absolute $04;  // ADC Data Register  Bytes
+  ADCL: byte absolute $04;  // ADC Data Register  Bytes
+  ADCH: byte absolute $05;  // ADC Data Register  Bytes;
+  ADCSR: byte absolute $06;  // The ADC Control and Status register
+  ADMUX: byte absolute $07;  // The ADC multiplexer Selection Register
+  ACSR: byte absolute $08;  // Analog Comparator Control And Status Register
+  PINB: byte absolute $16;  // Input Pins, Port B
+  DDRB: byte absolute $17;  // Data Direction Register, Port B
+  PORTB: byte absolute $18;  // Data Register, Port B
+  EECR: byte absolute $1C;  // EEPROM Control Register
+  EEDR: byte absolute $1D;  // EEPROM Data Register
+  EEAR: byte absolute $1E;  // EEPROM Read/Write Access
+  WDTCR: byte absolute $21;  // Watchdog Timer Control Register
+  SFIOR: byte absolute $2C;  // Special Function IO Register
+  OCR1B: byte absolute $2D;  // Output Compare Register
+  OCR1A: byte absolute $2E;  // Output Compare Register
+  TCNT1: byte absolute $2F;  // Timer/Counter Register
+  TCCR1: byte absolute $30;  // Timer/Counter Control Register
+  OSCCAL: byte absolute $31;  // Status Register
+  TCNT0: byte absolute $32;  // Timer Counter 0
+  TCCR0: byte absolute $33;  // Timer/Counter0 Control Register
+  MCUSR: byte absolute $34;  // MCU Status register
+  MCUCR: byte absolute $35;  // MCU Control Register
+  TIFR: byte absolute $38;  // Timer/Counter Interrupt Flag Register
+  TIMSK: byte absolute $39;  // Timer/Counter Interrupt Mask Register
+  GIFR: byte absolute $3A;  // General Interrupt Flag register
+  GIMSK: byte absolute $3B;  // General Interrupt Mask Register
+  SREG: byte absolute $3F;  // Status Register
+
+const
+  // The ADC Control and Status register
+  ADPS0 = $00;  // ADC  Prescaler Select Bits
+  ADPS1 = $01;  // ADC  Prescaler Select Bits
+  ADPS2 = $02;  // ADC  Prescaler Select Bits
+  ADIE = $03;  
+  ADIF = $04;  
+  ADFR = $05;  
+  ADSC = $06;  
+  ADEN = $07;  
+  // The ADC multiplexer Selection Register
+  MUX0 = $00;  // Analog Channel and Gain Selection Bits
+  MUX1 = $01;  // Analog Channel and Gain Selection Bits
+  MUX2 = $02;  // Analog Channel and Gain Selection Bits
+  ADLAR = $05;  
+  REFS0 = $06;  // Reference Selection Bits
+  REFS1 = $07;  // Reference Selection Bits
+  // Analog Comparator Control And Status Register
+  ACIS0 = $00;  // Analog Comparator Interrupt Mode Select bits
+  ACIS1 = $01;  // Analog Comparator Interrupt Mode Select bits
+  ACIE = $03;  
+  ACI = $04;  
+  ACO = $05;  
+  ACBG = $06;  
+  ACD = $07;  
+  // Data Register, Port B
+  PB0 = $00;  
+  PB1 = $01;  
+  PB2 = $02;  
+  PB3 = $03;  
+  PB4 = $04;  
+  // EEPROM Control Register
+  EERE = $00;  
+  EEWE = $01;  
+  EEMWE = $02;  
+  EERIE = $03;  
+  // Watchdog Timer Control Register
+  WDP0 = $00;  // Watch Dog Timer Prescaler bits
+  WDP1 = $01;  // Watch Dog Timer Prescaler bits
+  WDP2 = $02;  // Watch Dog Timer Prescaler bits
+  WDE = $03;  
+  WDTOE = $04;  
+  // Special Function IO Register
+  PSR0 = $00;  
+  PSR1 = $01;  
+  FOC1A = $02;  
+  // Timer/Counter Control Register
+  CS10 = $00;  // Clock Select Bits
+  CS11 = $01;  // Clock Select Bits
+  CS12 = $02;  // Clock Select Bits
+  CS13 = $03;  // Clock Select Bits
+  COM1A0 = $04;  // Compare Output Mode, Bits
+  COM1A1 = $05;  // Compare Output Mode, Bits
+  PWM1 = $06;  
+  CTC1 = $07;  
+  // Status Register
+  OSCCAL0 = $00;  // Oscillator Calibration 
+  OSCCAL1 = $01;  // Oscillator Calibration 
+  OSCCAL2 = $02;  // Oscillator Calibration 
+  OSCCAL3 = $03;  // Oscillator Calibration 
+  OSCCAL4 = $04;  // Oscillator Calibration 
+  OSCCAL5 = $05;  // Oscillator Calibration 
+  OSCCAL6 = $06;  // Oscillator Calibration 
+  OSCCAL7 = $07;  // Oscillator Calibration 
+  // Timer/Counter0 Control Register
+  CS00 = $00;  
+  CS01 = $01;  
+  CS02 = $02;  
+  // MCU Status register
+  PORF = $00;  
+  EXTRF = $01;  
+  BORF = $02;  
+  WDRF = $03;  
+  // MCU Control Register
+  ISC00 = $00;  // Interrupt Sense Control 0 bits
+  ISC01 = $01;  // Interrupt Sense Control 0 bits
+  SM0 = $03;  // Sleep Mode Select Bits
+  SM1 = $04;  // Sleep Mode Select Bits
+  SE = $05;  
+  PUD = $06;  
+  // Timer/Counter Interrupt Flag Register
+  TOV0 = $01;  
+  TOV1 = $02;  
+  OCF1A = $06;  
+  // Timer/Counter Interrupt Mask Register
+  TOIE0 = $01;  
+  TOIE1 = $02;  
+  OCIE1A = $06;  
+  // General Interrupt Flag register
+  PCIF = $05;  
+  INTF0 = $06;  
+  // General Interrupt Mask Register
+  PCIE = $05;  
+  INT0 = $06;  
+  // Status Register
+  C = $00;  
+  Z = $01;  
+  N = $02;  
+  V = $03;  
+  S = $04;  
+  H = $05;  
+  T = $06;  
+  I = $07;  
+
+
+implementation
+{$define RELBRANCHES}
+{$i avrcommon.inc}
+
+procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 1 External Interrupt 0
+procedure IO_PINS_ISR; external name 'IO_PINS_ISR'; // Interrupt 2 External Interrupt Request 0
+procedure TIMER1_COMP_ISR; external name 'TIMER1_COMP_ISR'; // Interrupt 3 Timer/Counter1 Compare Match
+procedure TIMER1_OVF_ISR; external name 'TIMER1_OVF_ISR'; // Interrupt 4 Timer/Counter1 Overflow
+procedure TIMER0_OVF_ISR; external name 'TIMER0_OVF_ISR'; // Interrupt 5 Timer/Counter0 Overflow
+procedure EE_RDY_ISR; external name 'EE_RDY_ISR'; // Interrupt 6 EEPROM Ready
+procedure ANA_COMP_ISR; external name 'ANA_COMP_ISR'; // Interrupt 7 Analog Comparator
+procedure ADC_ISR; external name 'ADC_ISR'; // Interrupt 8 ADC Conversion Ready
+
+procedure _FPC_start; assembler; nostackframe;
+label
+  _start;
+asm
+  .init
+  .globl _start
+
+  rjmp _start
+  rjmp INT0_ISR
+  rjmp IO_PINS_ISR
+  rjmp TIMER1_COMP_ISR
+  rjmp TIMER1_OVF_ISR
+  rjmp TIMER0_OVF_ISR
+  rjmp EE_RDY_ISR
+  rjmp ANA_COMP_ISR
+  rjmp ADC_ISR
+
+  {$i start_noram.inc}
+
+  .weak INT0_ISR
+  .weak IO_PINS_ISR
+  .weak TIMER1_COMP_ISR
+  .weak TIMER1_OVF_ISR
+  .weak TIMER0_OVF_ISR
+  .weak EE_RDY_ISR
+  .weak ANA_COMP_ISR
+  .weak ADC_ISR
+
+  .set INT0_ISR, Default_IRQ_handler
+  .set IO_PINS_ISR, Default_IRQ_handler
+  .set TIMER1_COMP_ISR, Default_IRQ_handler
+  .set TIMER1_OVF_ISR, Default_IRQ_handler
+  .set TIMER0_OVF_ISR, Default_IRQ_handler
+  .set EE_RDY_ISR, Default_IRQ_handler
+  .set ANA_COMP_ISR, Default_IRQ_handler
+  .set ADC_ISR, Default_IRQ_handler
+end;
+
+end.
avr1-controllers.patch (18,335 bytes)   

Florian

2020-02-09 11:51

administrator   ~0120964

Thanks, applied.

Christo Crause

2020-02-09 14:14

reporter   ~0120968

Thanks Florian.

Issue History

Date Modified Username Field Change
2020-02-09 11:06 Christo Crause New Issue
2020-02-09 11:06 Christo Crause File Added: avr1-controllers.patch
2020-02-09 11:51 Florian Assigned To => Florian
2020-02-09 11:51 Florian Status new => resolved
2020-02-09 11:51 Florian Resolution open => fixed
2020-02-09 11:51 Florian Fixed in Version => 3.3.1
2020-02-09 11:51 Florian Fixed in Revision => 44136
2020-02-09 11:51 Florian FPCTarget => -
2020-02-09 11:51 Florian Note Added: 0120964
2020-02-09 14:14 Christo Crause Status resolved => closed
2020-02-09 14:14 Christo Crause Note Added: 0120968