View Issue Details
| ID | Project | Category | View Status | Date Submitted | Last Update |
|---|---|---|---|---|---|
| 0037527 | FPC | Compiler | public | 2020-08-09 13:53 | 2020-12-02 06:40 |
| Reporter | avk | Assigned To | |||
| Priority | high | Severity | crash | Reproducibility | always |
| Status | new | Resolution | open | ||
| Platform | x86_64 | ||||
| Product Version | 3.3.1 | ||||
| Summary | 0037527: X86_64 code optimization | ||||
| Description | In some cases, when using optimization level 2 and above, FPC generates a completely inoperable code (seemingly starting with revision 45801). Unfortunately, I have no other example besides the one attached. | ||||
| Tags | No tags attached. | ||||
| Fixed in Revision | |||||
| FPCOldBugId | |||||
| FPCTarget | - | ||||
| Attached Files |
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What do you mean by 'inoperable' exactly? Does it not run at all or is it dead code etc? |
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It crashes with AV. |
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I'd take a look myself, but my Intel laptop is out of commission until further notice. However, if you can help me a bit, can you add the custom options "-a" and "-al" and supply the generated .s file (assembly dump), and mark where it crashes in your code (Just a line number in the Pascal source will do), I might be able to spot something and help someone else to make a fix... if they haven't found the problem already! |
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Yes, sure. According to the debugger, the AV occurs on line 361 of the timsort unit. |
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Any news? |
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My apologies for the delay - my time has been recently focused on a programming contract and also on some events outside of software development. I'll start looking at it soon. |
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BTW, compiling example with -O3 -OoNOREGVAR produces a workable code. |
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How does the patch over at 0038129 affect it? |
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It still crash with AV but works ok with '-OoNOREGVAR' switch. |
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Aah, drat! Okay, back to work. |
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Okay, analysing the disassembly and the virtual registers (before they are allocated by the compiler), at a certain point, the compiler seems to get confused and forget which real register has been assigned to a virtual register. In the attached file, on line 3553, is "addsd 16(%ireg29q,%ireg63q),%mreg33md". Up until this point, when fully compiled, %rdx is assigned to %ireg29q, but at this instruction (and the next addsd instruction, although execution doesn't get that far), %ireg29q is suddenly replaced with %rax instead, which is erroneous because %rax is also assigned to %ireg63q, hence the command becomes "addsd 16(%rax,%rax,1),%xmm0, which is very much incorrect. On another note (also occurs on -O3), Common Subexpression Elimination (CSE) misses the fact that "mov %r12,%rax; shl $5,%rax" appears multiple times. (Removing "inline" from TVec4.Less erases the error, but this is very much not ideal) |
| Date Modified | Username | Field | Change |
|---|---|---|---|
| 2020-08-09 13:53 | avk | New Issue | |
| 2020-08-09 13:53 | avk | File Added: ts_test.zip | |
| 2020-08-09 14:01 | J. Gareth Moreton | Note Added: 0124692 | |
| 2020-08-09 14:32 | avk | Note Added: 0124693 | |
| 2020-08-09 19:31 | J. Gareth Moreton | Priority | normal => high |
| 2020-08-09 19:31 | J. Gareth Moreton | Severity | minor => crash |
| 2020-08-09 19:31 | J. Gareth Moreton | Platform | x84_64 => x86_64 |
| 2020-08-09 19:31 | J. Gareth Moreton | FPCTarget | => - |
| 2020-08-09 19:35 | J. Gareth Moreton | Note Added: 0124704 | |
| 2020-08-10 09:13 | avk | Note Added: 0124711 | |
| 2020-08-10 09:13 | avk | File Added: asm.zip | |
| 2020-09-10 12:25 | avk | Note Added: 0125459 | |
| 2020-09-13 22:07 | J. Gareth Moreton | Note Added: 0125531 | |
| 2020-11-26 16:15 | J. Gareth Moreton | Relationship added | related to 0038129 |
| 2020-12-01 16:34 | avk | Note Added: 0127300 | |
| 2020-12-01 21:20 | J. Gareth Moreton | Note Added: 0127308 | |
| 2020-12-02 03:26 | Do-wan Kim | Note Added: 0127313 | |
| 2020-12-02 04:25 | J. Gareth Moreton | Note Added: 0127314 | |
| 2020-12-02 06:39 | J. Gareth Moreton | Note Added: 0127315 | |
| 2020-12-02 06:39 | J. Gareth Moreton | File Added: timsort.s | |
| 2020-12-02 06:40 | J. Gareth Moreton | Note Edited: 0127315 | View Revisions |
