RISC-V Embedded, compiler produces incorrect code for div operator.
Original Reporter info from Mantis: Bernd
-
Reporter name: Bernd
Original Reporter info from Mantis: Bernd
- Reporter name: Bernd
Description:
The attached program fails, because the compiler produces incorrect code for the div operator.
The program is compiled with following options:
ppcrossrv32 -CpRV32IMAC -Tembedded -WpGD32VF103CB -k-melf32lriscv -B -al -O2 test.pas
The relevant code is assembled to:
.globl P$TEST_$$_RUN P$TEST_$$_RUN: # [test.pas] # [7] begin addi x2,x2,-8 sw x1,4(x2) sw x8,0(x2) addi x8,x2,8 addi x2,x2,-60 # Var m located at x8-56, size=OS_32 # Var m1 located at x8-60, size=OS_32 # [8] m:= 1; addi x10,x0,1 sw x10,-56(x8) # [9] m1:= 200; addi x10,x0,200 sw x10,-60(x8) # [10] m1:= m div 10; lw x11,-56(x8) addi x10,x0,10 divu x10,x11,x10 &LtPos;&LtPos;&LtPos;&LtPos;< the divu result is located in x10 (x10:= x11 div x10) sw x11,-60(x8) &LtPos;&LtPos;&LtPos;&LtPos;< but x11 is written to the local variable m1 # [11] if m1 > 0 then begin lw x11,-60(x8) addi x10,x0,0 # Peephole SltuB2B performed bgeu x10,x11,.Lj6 # CPU RV32IMAC # [14] nop; nop # CPU RV32IMAC .Lj6: # [17] end;
I think, either divu should use x11 instead of x10 for the result, or the following sw instruction should use the register x10 instead of x11 as source.
Mantis conversion info:
- Mantis ID: 37743
- OS: Embedded
- Build: 46803
- Platform: RISC-V
- Version: 3.3.1
- Fixed in version: 3.3.1
- Fixed in revision: 46859 (#7f8f7339)