AVR [patch] Code generator incorrectly generates LDD instruction for avrtiny
Original Reporter info from Mantis: ccrause @ccrause
-
Reporter name: Christo Crause
Original Reporter info from Mantis: ccrause @ccrause
- Reporter name: Christo Crause
Description:
When compiling the test program below for avrtiny subarch (e.g.attiny10) an assembler error is generated: illegal opcode ld for mcu avrtiny. The generated assembler for the assignment:
# [15] wport := w;
ldi r30,lo8(U_sPsTEST_ss_W)
ldi r31,hi8(U_sPsTEST_ss_W)
ldd r16,Z+1
out 33,r16
ld r16,Z+
out 32,r16
It seems that the SrcQuickRef variable in cgcpu is not set true for avrtiny because of the "and (source.symbol=nil)" check on line 2533 in cgcpu.pas.
This extra check is also done on line 2555 for the destination, which forces loading/storing using two sets of index registers instead of the more compact use of LDS/STS. Removing this check from line 2555 results in more compact code for the lines "w := d1;" and "d1 := d;".
It is not clear to me whether these two change will cause problems in other situations. The other assignments in the test program below is unaffected by this patch.
Steps to reproduce:
program test;
var
w: word;
wport: word absolute $20;
d, d1: dword;
procedure dummy; alias: 'INT0_ISR'; interrupt;
begin
d := w;
w := d1;
end;
begin
wport := w;
d := wport;
d1 := d;
end.
Mantis conversion info:
- Mantis ID: 37929
- Version: 3.3.1
- Fixed in version: 3.3.1
- Fixed in revision: 47118 (#fa543359)