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IDProjectCategoryView StatusLast Update
0038961FPCCompilerpublic2021-06-06 19:09
ReporterChristo Crause Assigned ToFlorian  
PrioritynormalSeverityminorReproducibilityN/A
Status closedResolutionfixed 
Product Version3.3.1 
Fixed in Version3.3.1 
Summary0038961: AVR [patch] Minor editing fixes
DescriptionThe attached patch fixes the following formatting and spelling problems in the AVR compiler files:
- Change spelling of AM_PREDRECEMENT to AM_PREDECREMENT
- Fix multiline comment style to use {}
- Fix indenting of code in method tcgavr.g_concatcopy

No functionality should be modified by this patch.
TagsNo tags attached.
Fixed in Revision49474
FPCOldBugId
FPCTarget-
Attached Files

Activities

Christo Crause

2021-06-04 06:25

reporter  

minorfixes.patch (8,965 bytes)   
Index: compiler/avr/agavrgas.pas
===================================================================
--- compiler/avr/agavrgas.pas	(revision 49473)
+++ compiler/avr/agavrgas.pas	(working copy)
@@ -96,7 +96,7 @@
                 internalerror(2011021707)
               else if base<>NR_NO then
                 begin
-                  if addressmode=AM_PREDRECEMENT then
+                  if addressmode=AM_PREDECREMENT then
                     s:='-';
 
                   case base of
Index: compiler/avr/cgcpu.pas
===================================================================
--- compiler/avr/cgcpu.pas	(revision 49473)
+++ compiler/avr/cgcpu.pas	(working copy)
@@ -1374,12 +1374,11 @@
            end;
          if not conv_done then
            begin
-             // CC
-             // Write to 16 bit ioreg, first high byte then low byte
-             // sequence required for 16 bit timer registers
-             // See e.g. atmega328p manual para 15.3 Accessing 16 bit registers
-             // Avrxmega3: write low byte first then high byte
-             // See e.g. megaAVR-0 family data sheet 7.5.6 Accessing 16-bit registers
+             { Write to 16 bit ioreg, first high byte then low byte
+               sequence required for 16 bit timer registers
+               See e.g. atmega328p manual para 15.3 Accessing 16 bit registers
+               Avrxmega3: write low byte first then high byte
+               See e.g. megaAVR-0 family data sheet 7.5.6 Accessing 16-bit registers }
              if (current_settings.cputype <> cpu_avrxmega3) and
                (fromsize in [OS_16, OS_S16]) and QuickRef and addr_is_io_register(href.offset) then
                begin
@@ -2608,22 +2607,21 @@
                 dstref:=dest;
               end;
 
-              // CC
-              // If dest is an ioreg and size = 16 bit then
-              // write high byte first, then low byte
-              // but not for avrxmega3
-              if (len = 2) and DestQuickRef and (current_settings.cputype <> cpu_avrxmega3) and
-                  addr_is_io_register(dest.offset) then
-                begin
-                  // If src is also a 16 bit ioreg then read low byte then high byte
-                  if SrcQuickRef and addr_is_io_register(srcref.offset) then
-                    begin
-                      // First read source into temp registers
-                      tmpreg:=getintregister(list, OS_16);
-                      list.concat(taicpu.op_reg_ref(GetLoad(srcref),tmpreg,srcref));
-                      inc(srcref.offset);
-                      tmpreg2:=GetNextReg(tmpreg);
-                      list.concat(taicpu.op_reg_ref(GetLoad(srcref),tmpreg2,srcref));
+            { If dest is an ioreg and size = 16 bit then
+              write high byte first, then low byte
+              but not for avrxmega3 }
+            if (len = 2) and DestQuickRef and (current_settings.cputype <> cpu_avrxmega3) and
+                addr_is_io_register(dest.offset) then
+              begin
+                // If src is also a 16 bit ioreg then read low byte then high byte
+                if SrcQuickRef and addr_is_io_register(srcref.offset) then
+                  begin
+                    // First read source into temp registers
+                    tmpreg:=getintregister(list, OS_16);
+                    list.concat(taicpu.op_reg_ref(GetLoad(srcref),tmpreg,srcref));
+                    inc(srcref.offset);
+                    tmpreg2:=GetNextReg(tmpreg);
+                    list.concat(taicpu.op_reg_ref(GetLoad(srcref),tmpreg2,srcref));
 
                     // then move temp registers to dest in reverse order
                     inc(dstref.offset);
@@ -2637,7 +2635,7 @@
                       predecrement version of LD with pre-incremented pointer  }
                     if current_settings.cputype = cpu_avrtiny then
                       begin
-                        srcref.addressmode:=AM_PREDRECEMENT;
+                        srcref.addressmode:=AM_PREDECREMENT;
                         list.concat(taicpu.op_reg_const(A_SUBI,srcref.base,-2));
                         list.concat(taicpu.op_reg_const(A_SBCI,GetNextReg(srcref.base),$FF));
                       end
@@ -2658,7 +2656,7 @@
                     if not(SrcQuickRef) and (current_settings.cputype <> cpu_avrtiny) then
                       srcref.addressmode:=AM_POSTINCREMENT
                     else if current_settings.cputype = cpu_avrtiny then
-                      srcref.addressmode:=AM_PREDRECEMENT
+                      srcref.addressmode:=AM_PREDECREMENT
                     else
                       srcref.addressmode:=AM_UNCHANGED;
 
@@ -2695,17 +2693,18 @@
                   if DestQuickRef then
                     inc(dstref.offset);
                 end;
-              if not(SrcQuickRef) then
-                begin
-                  ungetcpuregister(list,srcref.base);
-                  ungetcpuregister(list,TRegister(ord(srcref.base)+1));
-                end;
-              if not(DestQuickRef) then
-                begin
-                  ungetcpuregister(list,dstref.base);
-                  ungetcpuregister(list,TRegister(ord(dstref.base)+1));
-                end;
-            end;
+
+            if not(SrcQuickRef) then
+              begin
+                ungetcpuregister(list,srcref.base);
+                ungetcpuregister(list,TRegister(ord(srcref.base)+1));
+              end;
+            if not(DestQuickRef) then
+              begin
+                ungetcpuregister(list,dstref.base);
+                ungetcpuregister(list,TRegister(ord(dstref.base)+1));
+              end;
+          end;
         end;
 
 
Index: compiler/avr/cpubase.pas
===================================================================
--- compiler/avr/cpubase.pas	(revision 49473)
+++ compiler/avr/cpubase.pas	(working copy)
@@ -160,7 +160,7 @@
                                 Operands
 *****************************************************************************}
 
-      taddressmode = (AM_UNCHANGED,AM_POSTINCREMENT,AM_PREDRECEMENT);
+      taddressmode = (AM_UNCHANGED,AM_POSTINCREMENT,AM_PREDECREMENT);
 
 {*****************************************************************************
                                  Constants
Index: compiler/avr/raavrgas.pas
===================================================================
--- compiler/avr/raavrgas.pas	(revision 49473)
+++ compiler/avr/raavrgas.pas	(working copy)
@@ -349,7 +349,7 @@
                 begin
                   { Special handling of predecrement addressing }
                   oper.InitRef;
-                  oper.opr.ref.addressmode:=AM_PREDRECEMENT;
+                  oper.opr.ref.addressmode:=AM_PREDECREMENT;
 
                   consume(AS_MINUS);
 
Index: compiler/avr/raavr.pas
===================================================================
--- compiler/avr/raavr.pas	(revision 49473)
+++ compiler/avr/raavr.pas	(working copy)
@@ -164,13 +164,13 @@
        // Perhaps handle separately with a check on sub-architecture? Range check only important if smaller instruction code selected on larger arch
        (numOperands: (1 shl 2); Operands: ((typ: top_reg; rt: rt_all), (typ: top_const; max: 65535; min: 0))),
        // A_LD
-       (numOperands: (1 shl 2); Operands: ((typ: top_reg; rt: rt_all), (typ: top_reg; rt: rt_XYZ; am: [AM_UNCHANGED, AM_POSTINCREMENT, AM_PREDRECEMENT]))),
+       (numOperands: (1 shl 2); Operands: ((typ: top_reg; rt: rt_all), (typ: top_reg; rt: rt_XYZ; am: [AM_UNCHANGED, AM_POSTINCREMENT, AM_PREDECREMENT]))),
        // A_LDD
        (numOperands: (1 shl 2); Operands: ((typ: top_reg; rt: rt_all), (typ: top_reg; rt: rt_YZ; am: [AM_UNCHANGED]; minconst: 0; maxconst: 63))),
        // A_STS TODO: See LDS above
        (numOperands: (1 shl 2); Operands: ((typ: top_const; max: 65535; min: 0), (typ: top_reg; rt: rt_all))),
        // A_ST
-       (numOperands: (1 shl 2); Operands: ((typ: top_reg; rt: rt_XYZ; am: [AM_UNCHANGED, AM_POSTINCREMENT, AM_PREDRECEMENT]), (typ: top_reg; rt: rt_all))),
+       (numOperands: (1 shl 2); Operands: ((typ: top_reg; rt: rt_XYZ; am: [AM_UNCHANGED, AM_POSTINCREMENT, AM_PREDECREMENT]), (typ: top_reg; rt: rt_all))),
        // A_STD
        (numOperands: (1 shl 2); Operands: ((typ: top_reg; rt: rt_YZ; am: [AM_UNCHANGED]; minconst: 0; maxconst: 63), (typ: top_reg; rt: rt_all))),
        // A_LPM
@@ -348,7 +348,7 @@
 
                         if not (err) and not(AM_UNCHANGED in AVRInstrConstraint[opcode].Operands[i].am) and
                           ((AM_POSTINCREMENT in AVRInstrConstraint[opcode].Operands[i].am) or
-                           (AM_PREDRECEMENT in AVRInstrConstraint[opcode].Operands[i].am)) then
+                           (AM_PREDECREMENT in AVRInstrConstraint[opcode].Operands[i].am)) then
                           err := not opregasref;
 
                         if not(err) and opregasref then
minorfixes.patch (8,965 bytes)   

Florian

2021-06-04 20:16

administrator   ~0131154

Thanks, applied.

Christo Crause

2021-06-06 19:09

reporter   ~0131189

Thanks!

Issue History

Date Modified Username Field Change
2021-06-04 06:25 Christo Crause New Issue
2021-06-04 06:25 Christo Crause File Added: minorfixes.patch
2021-06-04 20:16 Florian Assigned To => Florian
2021-06-04 20:16 Florian Status new => resolved
2021-06-04 20:16 Florian Resolution open => fixed
2021-06-04 20:16 Florian Fixed in Version => 3.3.1
2021-06-04 20:16 Florian Fixed in Revision => 49474
2021-06-04 20:16 Florian FPCTarget => -
2021-06-04 20:16 Florian Note Added: 0131154
2021-06-06 19:09 Christo Crause Status resolved => closed
2021-06-06 19:09 Christo Crause Note Added: 0131189